//
// The LLVM Compiler Infrastructure
//
-// This file was developed by the LLVM research group and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// in the target machine. String n will become the "name" of the register.
class Register<string n> {
string Namespace = "";
+ string AsmName = n;
string Name = n;
// SpillSize - If this value is set to a non-zero value, it is the size in
// not [AX, AH, AL].
list<Register> SubRegs = [];
- // DwarfNumber - Number used internally by gcc/gdb to identify the register.
+ // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register.
// These values can be determined by locating the <target>.h file in the
// directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The
// order of these names correspond to the enumeration used by gcc. A value of
- // -1 indicates that the gcc number is undefined.
- int DwarfNumber = -1;
+ // -1 indicates that the gcc number is undefined and -2 that register number
+ // is invalid for this mode/flavour.
+ list<int> DwarfNumbers = [];
}
// RegisterWithSubRegs - This can be used to define instances of Register which
// to the register numbering used by gcc and gdb. These values are used by a
// debug information writer (ex. DwarfWriter) to describe where values may be
// located during execution.
-class DwarfRegNum<int N> {
- // DwarfNumber - Number used internally by gcc/gdb to identify the register.
+class DwarfRegNum<list<int> Numbers> {
+ // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register.
// These values can be determined by locating the <target>.h file in the
// directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The
// order of these names correspond to the enumeration used by gcc. A value of
- // -1 indicates that the gcc number is undefined.
- int DwarfNumber = N;
+ // -1 indicates that the gcc number is undefined and -2 that register number is
+ // invalid for this mode/flavour.
+ list<int> DwarfNumbers = Numbers;
}
//===----------------------------------------------------------------------===//
// the Target/TargetInstrInfo.h file.
//
class Instruction {
- string Name = ""; // The opcode string for this instruction
string Namespace = "";
dag OutOperandList; // An dag containing the MI def operand list.
// instruction.
bit isReturn = 0; // Is this instruction a return instruction?
bit isBranch = 0; // Is this instruction a branch instruction?
+ bit isIndirectBranch = 0; // Is this instruction an indirect branch?
bit isBarrier = 0; // Can control flow fall through this instruction?
bit isCall = 0; // Is this instruction a call instruction?
- bit isLoad = 0; // Is this instruction a load instruction?
- bit isStore = 0; // Is this instruction a store instruction?
+ bit isSimpleLoad = 0; // Is this just a load instruction?
+ bit mayLoad = 0; // Is it possible for this inst to read memory?
+ bit mayStore = 0; // Is it possible for this inst to write memory?
+ bit isImplicitDef = 0; // Is this instruction an implicit def instruction?
bit isTwoAddress = 0; // Is this a two address instruction?
bit isConvertibleToThreeAddress = 0; // Can this 2-addr instruction promote?
bit isCommutable = 0; // Is this 3 operand instruction commutable?
bit usesCustomDAGSchedInserter = 0; // Pseudo instr needing special help.
bit hasCtrlDep = 0; // Does this instruction r/w ctrl-flow chains?
bit isNotDuplicable = 0; // Is it unsafe to duplicate this instruction?
+
+ // Side effect flags - When set, the flags have these meanings:
+ //
+ // hasSideEffects - The instruction has side effects that are not
+ // captured by any operands of the instruction or other flags.
+ // mayHaveSideEffects - Some instances of the instruction can have side
+ // effects. The virtual method "isReallySideEffectFree" is called to
+ // determine this. Load instructions are an example of where this is
+ // useful. In general, loads always have side effects. However, loads from
+ // constant pools don't. Individual back ends make this determination.
+ // neverHasSideEffects - Set on an instruction with no pattern if it has no
+ // side effects.
+ bit hasSideEffects = 0;
+ bit mayHaveSideEffects = 0;
+ bit neverHasSideEffects = 0;
InstrItinClass Itinerary = NoItinerary;// Execution steps used for scheduling.
def i32imm : Operand<i32>;
def i64imm : Operand<i64>;
+def f32imm : Operand<f32>;
+def f64imm : Operand<f64>;
+
/// zero_reg definition - Special node to stand for the zero register.
///
def zero_reg;
}
def LABEL : Instruction {
let OutOperandList = (ops);
- let InOperandList = (ops i32imm:$id);
+ let InOperandList = (ops i32imm:$id, i32imm:$flavor);
+ let AsmString = "";
+ let Namespace = "TargetInstrInfo";
+ let hasCtrlDep = 1;
+}
+def DECLARE : Instruction {
+ let OutOperandList = (ops);
+ let InOperandList = (ops variable_ops);
let AsmString = "";
let Namespace = "TargetInstrInfo";
let hasCtrlDep = 1;
}
def EXTRACT_SUBREG : Instruction {
- let OutOperandList = (ops variable_ops);
+ let OutOperandList = (ops variable_ops);
let InOperandList = (ops variable_ops);
let AsmString = "";
let Namespace = "TargetInstrInfo";
+ let neverHasSideEffects = 1;
}
def INSERT_SUBREG : Instruction {
let OutOperandList = (ops variable_ops);
let InOperandList = (ops variable_ops);
let AsmString = "";
let Namespace = "TargetInstrInfo";
+ let neverHasSideEffects = 1;
}
//===----------------------------------------------------------------------===//
projects / oota-llvm.git / blobdiff