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[oota-llvm.git] / lib / Target / Target.td

diff --git a/lib/Target/Target.td b/lib/Target/Target.td
index 4c28f99b6f2430927a8ff69892a1787be7e91f80..cebac7a263650b8b01f7ea5043b73025fe7a3c74 100644 (file)
--- a/lib/Target/Target.td
+++ b/lib/Target/Target.td
@@ -2,8 +2,8 @@
 // 
 //                     The LLVM Compiler Infrastructure
 //
-// This file was developed by the LLVM research group and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
 // 
 //===----------------------------------------------------------------------===//
 //
@@ -25,6 +25,7 @@ class RegisterClass; // Forward def
 // in the target machine.  String n will become the "name" of the register.
 class Register<string n> {
   string Namespace = "";
+  string AsmName = n;
   string Name = n;
 
   // SpillSize - If this value is set to a non-zero value, it is the size in
@@ -156,7 +157,6 @@ class Predicate; // Forward def
 // the Target/TargetInstrInfo.h file.
 //
 class Instruction {
-  string Name = "";         // The opcode string for this instruction
   string Namespace = "";
 
   dag OutOperandList;       // An dag containing the MI def operand list.
@@ -190,8 +190,10 @@ class Instruction {
   bit isIndirectBranch = 0; // Is this instruction an indirect branch?
   bit isBarrier    = 0;     // Can control flow fall through this instruction?
   bit isCall       = 0;     // Is this instruction a call instruction?
-  bit isLoad       = 0;     // Is this instruction a load instruction?
-  bit isStore      = 0;     // Is this instruction a store instruction?
+  bit isSimpleLoad = 0;     // Is this just a load instruction?
+  bit mayLoad      = 0;     // Is it possible for this inst to read memory?
+  bit mayStore     = 0;     // Is it possible for this inst to write memory?
+  bit isImplicitDef = 0;    // Is this instruction an implicit def instruction?
   bit isTwoAddress = 0;     // Is this a two address instruction?
   bit isConvertibleToThreeAddress = 0;  // Can this 2-addr instruction promote?
   bit isCommutable = 0;     // Is this 3 operand instruction commutable?
@@ -202,6 +204,21 @@ class Instruction {
   bit usesCustomDAGSchedInserter = 0; // Pseudo instr needing special help.
   bit hasCtrlDep   = 0;     // Does this instruction r/w ctrl-flow chains?
   bit isNotDuplicable = 0;  // Is it unsafe to duplicate this instruction?
+
+  // Side effect flags - When set, the flags have these meanings:
+  //
+  //  hasSideEffects - The instruction has side effects that are not
+  //    captured by any operands of the instruction or other flags.
+  //  mayHaveSideEffects  - Some instances of the instruction can have side
+  //    effects. The virtual method "isReallySideEffectFree" is called to
+  //    determine this. Load instructions are an example of where this is
+  //    useful. In general, loads always have side effects. However, loads from
+  //    constant pools don't. Individual back ends make this determination.
+  //  neverHasSideEffects - Set on an instruction with no pattern if it has no
+  //    side effects.
+  bit hasSideEffects = 0;
+  bit mayHaveSideEffects = 0;
+  bit neverHasSideEffects = 0;
   
   InstrItinClass Itinerary = NoItinerary;// Execution steps used for scheduling.
 
@@ -261,6 +278,9 @@ def i16imm : Operand<i16>;
 def i32imm : Operand<i32>;
 def i64imm : Operand<i64>;
 
+def f32imm : Operand<f32>;
+def f64imm : Operand<f64>;
+
 /// zero_reg definition - Special node to stand for the zero register.
 ///
 def zero_reg;
@@ -318,22 +338,31 @@ def INLINEASM : Instruction {
 }
 def LABEL : Instruction {
   let OutOperandList = (ops);
-  let InOperandList = (ops i32imm:$id);
+  let InOperandList = (ops i32imm:$id, i32imm:$flavor);
+  let AsmString = "";
+  let Namespace = "TargetInstrInfo";
+  let hasCtrlDep = 1;
+}
+def DECLARE : Instruction {
+  let OutOperandList = (ops);
+  let InOperandList = (ops variable_ops);
   let AsmString = "";
   let Namespace = "TargetInstrInfo";
   let hasCtrlDep = 1;
 }
 def EXTRACT_SUBREG : Instruction {
-        let OutOperandList = (ops variable_ops);
+  let OutOperandList = (ops variable_ops);
   let InOperandList = (ops variable_ops);
   let AsmString = "";
   let Namespace = "TargetInstrInfo";
+  let neverHasSideEffects = 1;
 }
 def INSERT_SUBREG : Instruction {
         let OutOperandList = (ops variable_ops);
   let InOperandList = (ops variable_ops);
   let AsmString = "";
   let Namespace = "TargetInstrInfo";
+  let neverHasSideEffects = 1;
 }
 
 //===----------------------------------------------------------------------===//