Add comment.

[oota-llvm.git] / lib / Target / Target.td

diff --git a/lib/Target/Target.td b/lib/Target/Target.td
index d155e713c0db95987971c2f00d0c26b48ccaf419..cebac7a263650b8b01f7ea5043b73025fe7a3c74 100644 (file)
--- a/lib/Target/Target.td
+++ b/lib/Target/Target.td
@@ -25,6 +25,7 @@ class RegisterClass; // Forward def
 // in the target machine.  String n will become the "name" of the register.
 class Register<string n> {
   string Namespace = "";
+  string AsmName = n;
   string Name = n;
 
   // SpillSize - If this value is set to a non-zero value, it is the size in
@@ -277,6 +278,9 @@ def i16imm : Operand<i16>;
 def i32imm : Operand<i32>;
 def i64imm : Operand<i64>;
 
+def f32imm : Operand<f32>;
+def f64imm : Operand<f64>;
+
 /// zero_reg definition - Special node to stand for the zero register.
 ///
 def zero_reg;
@@ -334,13 +338,20 @@ def INLINEASM : Instruction {
 }
 def LABEL : Instruction {
   let OutOperandList = (ops);
-  let InOperandList = (ops i32imm:$id);
+  let InOperandList = (ops i32imm:$id, i32imm:$flavor);
+  let AsmString = "";
+  let Namespace = "TargetInstrInfo";
+  let hasCtrlDep = 1;
+}
+def DECLARE : Instruction {
+  let OutOperandList = (ops);
+  let InOperandList = (ops variable_ops);
   let AsmString = "";
   let Namespace = "TargetInstrInfo";
   let hasCtrlDep = 1;
 }
 def EXTRACT_SUBREG : Instruction {
-        let OutOperandList = (ops variable_ops);
+  let OutOperandList = (ops variable_ops);
   let InOperandList = (ops variable_ops);
   let AsmString = "";
   let Namespace = "TargetInstrInfo";