Merge PPCJITInfo.h and PPC32JITInfo.h. Note that the PowerPCJITInfo

[oota-llvm.git] / lib / Target / TargetInstrInfo.cpp

diff --git a/lib/Target/TargetInstrInfo.cpp b/lib/Target/TargetInstrInfo.cpp
index f377d67b66f7606be0ee3c2fb0709ba027756010..930ca1f490db767568119d239c4f46f96e66cb3d 100644 (file)
--- a/lib/Target/TargetInstrInfo.cpp
+++ b/lib/Target/TargetInstrInfo.cpp
@@ -1,12 +1,13 @@
 //===-- TargetInstrInfo.cpp - Target Instruction Information --------------===//
-// 
+//
 //                     The LLVM Compiler Infrastructure
 //
 // This file was developed by the LLVM research group and is distributed under
 // the University of Illinois Open Source License. See LICENSE.TXT for details.
-// 
+//
 //===----------------------------------------------------------------------===//
 //
+// This file implements the TargetInstrInfo class.
 //
 //===----------------------------------------------------------------------===//
 
@@ -14,29 +15,32 @@
 #include "llvm/CodeGen/MachineInstr.h"
 #include "llvm/Constant.h"
 #include "llvm/DerivedTypes.h"
+using namespace llvm;
 
-// External object describing the machine instructions
-// Initialized only when the TargetMachine class is created
-// and reset when that class is destroyed.
-// 
-const TargetInstrDescriptor* TargetInstrDescriptors = 0;
-
+namespace llvm {
+  // External object describing the machine instructions Initialized only when
+  // the TargetMachine class is created and reset when that class is destroyed.
+  //
+  // FIXME: UGLY SPARCV9 HACK!
+  const TargetInstrDescriptor* TargetInstrDescriptors = 0;
+}
 
 TargetInstrInfo::TargetInstrInfo(const TargetInstrDescriptor* Desc,
-                                unsigned DescSize,
-                                unsigned NumRealOpCodes)
-  : desc(Desc), descSize(DescSize), numRealOpCodes(NumRealOpCodes) {
+                                 unsigned numOpcodes)
+  : desc(Desc), NumOpcodes(numOpcodes) {
   // FIXME: TargetInstrDescriptors should not be global
-  assert(TargetInstrDescriptors == NULL && desc != NULL);
-  TargetInstrDescriptors = desc;       // initialize global variable
+  assert(TargetInstrDescriptors == NULL && desc != NULL
+         && "TargetMachine data structure corrupt; maybe you tried to create another TargetMachine? (only one may exist in a program)");
+  TargetInstrDescriptors = desc; // initialize global variable
 }
 
 TargetInstrInfo::~TargetInstrInfo() {
-  TargetInstrDescriptors = NULL;       // reset global variable
+  TargetInstrDescriptors = NULL; // reset global variable
 }
 
+// FIXME: SPARCV9 SPECIFIC!
 bool TargetInstrInfo::constantFitsInImmedField(MachineOpCode opCode,
-                                              int64_t intValue) const {
+                                               int64_t intValue) const {
   // First, check if opCode has an immed field.
   bool isSignExtended;
   uint64_t maxImmedValue = maxImmedConstant(opCode, isSignExtended);
@@ -45,17 +49,24 @@ bool TargetInstrInfo::constantFitsInImmedField(MachineOpCode opCode,
       // NEED TO HANDLE UNSIGNED VALUES SINCE THEY MAY BECOME MUCH
       // SMALLER AFTER CASTING TO SIGN-EXTENDED int, short, or char.
       // See CreateUIntSetInstruction in SparcInstrInfo.cpp.
-      
+
       // Now check if the constant fits
       if (intValue <= (int64_t) maxImmedValue &&
-         intValue >= -((int64_t) maxImmedValue+1))
-       return true;
+          intValue >= -((int64_t) maxImmedValue+1))
+        return true;
     }
-  
+
   return false;
 }
 
-bool TargetInstrInfo::ConstantTypeMustBeLoaded(const Constant* CV) const {
-  assert(CV->getType()->isPrimitiveType() || isa<PointerType>(CV->getType()));
-  return !(CV->getType()->isIntegral() || isa<PointerType>(CV->getType()));
+// commuteInstruction - The default implementation of this method just exchanges
+// operand 1 and 2.
+MachineInstr *TargetInstrInfo::commuteInstruction(MachineInstr *MI) const {
+  assert(MI->getOperand(1).isRegister() && MI->getOperand(2).isRegister() &&
+         "This only knows how to commute register operands so far");
+  unsigned Reg1 = MI->getOperand(1).getReg();
+  unsigned Reg2 = MI->getOperand(1).getReg();
+  MI->SetMachineOperandReg(2, Reg1);
+  MI->SetMachineOperandReg(1, Reg2);
+  return MI;
 }