//===-- SchedInfo.cpp - Generic code to support target schedulers ----------==//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file was developed by the LLVM research group and is distributed under
+// the University of Illinois Open Source License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
//
// This file implements the generic part of a Scheduler description for a
// target. This functionality is defined in the llvm/Target/SchedInfo.h file.
//
//===----------------------------------------------------------------------===//
+#include "llvm/Config/alloca.h"
#include "llvm/Target/TargetSchedInfo.h"
#include "llvm/Target/TargetMachine.h"
+#include <algorithm>
+#include <iostream>
+using namespace llvm;
+
+resourceId_t llvm::CPUResource::nextId = 0;
+static std::vector<CPUResource*> *CPUResourceMap = 0;
+
+CPUResource::CPUResource(const std::string& resourceName, int maxUsers)
+ : rname(resourceName), rid(nextId++), maxNumUsers(maxUsers) {
+ if(!CPUResourceMap)
+ CPUResourceMap = new std::vector<CPUResource*>;
-resourceId_t MachineResource::nextId = 0;
+ //Put Resource in the map
+ CPUResourceMap->push_back(this);
+}
+
+///Get CPUResource if you only have the resource ID
+CPUResource* CPUResource::getCPUResource(resourceId_t id) {
+ return (*CPUResourceMap)[id];
+}
// Check if fromRVec and toRVec have *any* common entries.
// Assume the vectors are sorted in increasing order.
unsigned NumUsageDeltas,
unsigned NumIssueDeltas)
: target(tgt),
- numSchedClasses(NumSchedClasses), mii(& tgt.getInstrInfo()),
+ numSchedClasses(NumSchedClasses), mii(tgt.getInstrInfo()),
classRUsages(ClassRUsages), usageDeltas(UsageDeltas),
issueDeltas(IssueDeltas), numUsageDeltas(NumUsageDeltas),
numIssueDeltas(NumIssueDeltas)
TargetSchedInfo::computeInstrResources(const std::vector<InstrRUsage>&
instrRUForClasses)
{
- int numOpCodes = mii->getNumRealOpCodes();
+ int numOpCodes = mii->getNumOpcodes();
instrRUsages.resize(numOpCodes);
// First get the resource usage information from the class resource usages.
TargetSchedInfo::computeIssueGaps(const std::vector<InstrRUsage>&
instrRUForClasses)
{
- int numOpCodes = mii->getNumRealOpCodes();
+ int numOpCodes = mii->getNumOpcodes();
issueGaps.resize(numOpCodes);
conflictLists.resize(numOpCodes);
- assert(numOpCodes < (1 << MAX_OPCODE_SIZE) - 1
- && "numOpCodes invalid for implementation of class OpCodePair!");
-
// First, compute issue gaps between pairs of classes based on common
// resources usages for each class, because most instruction pairs will
// usually behave the same as their class.
//
- int classPairGaps[numSchedClasses][numSchedClasses];
+ int* classPairGaps =
+ static_cast<int*>(alloca(sizeof(int) * numSchedClasses * numSchedClasses));
for (InstrSchedClass fromSC=0; fromSC < numSchedClasses; fromSC++)
for (InstrSchedClass toSC=0; toSC < numSchedClasses; toSC++) {
int classPairGap = ComputeMinGap(instrRUForClasses[fromSC],
instrRUForClasses[toSC]);
- classPairGaps[fromSC][toSC] = classPairGap;
+ classPairGaps[fromSC*numSchedClasses + toSC] = classPairGap;
}
// Now, for each pair of instructions, use the class pair gap if both
for (MachineOpCode toOp=0; toOp < numOpCodes; toOp++) {
int instrPairGap =
(instrRUsages[fromOp].sameAsClass && instrRUsages[toOp].sameAsClass)
- ? classPairGaps[getSchedClass(fromOp)][getSchedClass(toOp)]
+ ? classPairGaps[getSchedClass(fromOp)*numSchedClasses + getSchedClass(toOp)]
: ComputeMinGap(instrRUsages[fromOp], instrRUsages[toOp]);
if (instrPairGap > 0) {
// Sort each resource usage vector by resourceId_t to speed up conflict
// checking
for (unsigned i=0; i < this->resourcesByCycle.size(); i++)
- sort(resourcesByCycle[i].begin(), resourcesByCycle[i].end());
+ std::sort(resourcesByCycle[i].begin(), resourcesByCycle[i].end());
}
// Add the extra resource usage requirements specified in the delta.