Add support for reading and writing pointersize/endianness to and from bytecode

[oota-llvm.git] / lib / Target / TargetSchedInfo.cpp

diff --git a/lib/Target/TargetSchedInfo.cpp b/lib/Target/TargetSchedInfo.cpp
index 40e822dc14b7baf4533a018e1d98958e14766042..d64652398ae7421eb8b7cb7e5220ecf127b4377b 100644 (file)
--- a/lib/Target/TargetSchedInfo.cpp
+++ b/lib/Target/TargetSchedInfo.cpp
@@ -5,15 +5,9 @@
 //
 //===----------------------------------------------------------------------===//
 
-#include "llvm/Target/MachineSchedInfo.h"
+#include "llvm/Target/TargetSchedInfo.h"
 #include "llvm/Target/TargetMachine.h"
 
-// External object describing the machine instructions
-// Initialized only when the TargetMachine class is created
-// and reset when that class is destroyed.
-// 
-const MachineInstrDescriptor* TargetInstrDescriptors = 0;
-
 resourceId_t MachineResource::nextId = 0;
 
 // Check if fromRVec and toRVec have *any* common entries.
@@ -75,17 +69,17 @@ ComputeMinGap(const InstrRUsage &fromRU,
 
 
 //---------------------------------------------------------------------------
-// class MachineSchedInfo
+// class TargetSchedInfo
 //     Interface to machine description for instruction scheduling
 //---------------------------------------------------------------------------
 
-MachineSchedInfo::MachineSchedInfo(const TargetMachine&    tgt,
-                                   int                     NumSchedClasses,
-                                   const InstrClassRUsage* ClassRUsages,
-                                   const InstrRUsageDelta* UsageDeltas,
-                                   const InstrIssueDelta*  IssueDeltas,
-                                   unsigned int                   NumUsageDeltas,
-                                   unsigned int                   NumIssueDeltas)
+TargetSchedInfo::TargetSchedInfo(const TargetMachine&    tgt,
+                                 int                     NumSchedClasses,
+                                 const InstrClassRUsage* ClassRUsages,
+                                 const InstrRUsageDelta* UsageDeltas,
+                                 const InstrIssueDelta*  IssueDeltas,
+                                 unsigned NumUsageDeltas,
+                                 unsigned NumIssueDeltas)
   : target(tgt),
     numSchedClasses(NumSchedClasses), mii(& tgt.getInstrInfo()),
     classRUsages(ClassRUsages), usageDeltas(UsageDeltas),
@@ -94,7 +88,7 @@ MachineSchedInfo::MachineSchedInfo(const TargetMachine&    tgt,
 {}
 
 void
-MachineSchedInfo::initializeResources()
+TargetSchedInfo::initializeResources()
 {
   assert(MAX_NUM_SLOTS >= (int)getMaxNumIssueTotal()
         && "Insufficient slots for static data! Increase MAX_NUM_SLOTS");
@@ -117,7 +111,7 @@ MachineSchedInfo::initializeResources()
 
 
 void
-MachineSchedInfo::computeInstrResources(const std::vector<InstrRUsage>&
+TargetSchedInfo::computeInstrResources(const std::vector<InstrRUsage>&
                                        instrRUForClasses)
 {
   int numOpCodes =  mii->getNumRealOpCodes();
@@ -147,7 +141,7 @@ MachineSchedInfo::computeInstrResources(const std::vector<InstrRUsage>&
 
 
 void
-MachineSchedInfo::computeIssueGaps(const std::vector<InstrRUsage>&
+TargetSchedInfo::computeIssueGaps(const std::vector<InstrRUsage>&
                                   instrRUForClasses)
 {
   int numOpCodes =  mii->getNumRealOpCodes();