This shouldn't be necessary

[oota-llvm.git] / lib / Target / TargetSchedule.td

diff --git a/lib/Target/TargetSchedule.td b/lib/Target/TargetSchedule.td
index 9b4ad022d8160979920f869742d1924bad69000b..38461c5a380ed79c8a356af6319714e603499c02 100644 (file)
--- a/lib/Target/TargetSchedule.td
+++ b/lib/Target/TargetSchedule.td
@@ -2,8 +2,8 @@
 // 
 //                     The LLVM Compiler Infrastructure
 //
-// This file was developed by James M. Laskey and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
 // 
 //===----------------------------------------------------------------------===//
 //
@@ -12,13 +12,6 @@
 //
 //===----------------------------------------------------------------------===//
 
-//===----------------------------------------------------------------------===//
-// Processor chip sets - These values represent each of the chip sets supported
-// by the scheduler.  Each Processor definition requires corresponding
-// instruction itineraries.
-//
-class Processor;
-
 //===----------------------------------------------------------------------===//
 // Processor functional unit - These values represent the function units
 // available across all chip sets for the target.  Eg., IntUnit, FPUnit, ...
@@ -35,8 +28,8 @@ class FuncUnit;
 // need to complete the stage.  Units represent the choice of functional units
 // that can be used to complete the stage.  Eg. IntUnit1, IntUnit2.
 //
-class InstrStage<int latency, list<FuncUnit> units> {
-  int Latency          = latency;     // length of stage in machine cycles
+class InstrStage<int cycles, list<FuncUnit> units> {
+  int Cycles          = cycles;       // length of stage in machine cycles
   list<FuncUnit> Units = units;       // choice of functional units
 }
 
@@ -54,6 +47,7 @@ class InstrStage<int latency, list<FuncUnit> units> {
 // instruction information.
 //
 class InstrItinClass;
+def NoItinerary : InstrItinClass;
 
 //===----------------------------------------------------------------------===//
 // Instruction itinerary data - These values provide a runtime map of an 
@@ -68,7 +62,11 @@ class InstrItinData<InstrItinClass Class, list<InstrStage> stages> {
 // Processor itineraries - These values represent the set of all itinerary
 // classes for a given chip set.
 //
-class ProcessorItineraries<Processor proc, list<InstrItinData> iid> {
-  Processor Proc = proc;
+class ProcessorItineraries<list<InstrItinData> iid> {
   list<InstrItinData> IID = iid;
 }
+
+// NoItineraries - A marker that can be used by processors without schedule
+// info.
+def NoItineraries : ProcessorItineraries<[]>;
+