Specify S registers as D registers' sub-registers.

[oota-llvm.git] / lib / Target / TargetSchedule.td

diff --git a/lib/Target/TargetSchedule.td b/lib/Target/TargetSchedule.td
index 2198c153f7b39d62f64482c0ffb668ef6398af07..8ac537f977a1266555833f545566170b0e1f9f42 100644 (file)
--- a/lib/Target/TargetSchedule.td
+++ b/lib/Target/TargetSchedule.td
@@ -47,6 +47,7 @@ class InstrStage<int cycles, list<FuncUnit> units> {
 // instruction information.
 //
 class InstrItinClass;
+def NoItinerary : InstrItinClass;
 
 //===----------------------------------------------------------------------===//
 // Instruction itinerary data - These values provide a runtime map of an 
@@ -64,3 +65,8 @@ class InstrItinData<InstrItinClass Class, list<InstrStage> stages> {
 class ProcessorItineraries<list<InstrItinData> iid> {
   list<InstrItinData> IID = iid;
 }
+
+// NoItineraries - A marker that can be used by processors without schedule
+// info.
+def NoItineraries : ProcessorItineraries<[]>;
+