Build arbitrary vector with more than 2 distinct scalar elements with a

[oota-llvm.git] / lib / Target / TargetSelectionDAG.td

diff --git a/lib/Target/TargetSelectionDAG.td b/lib/Target/TargetSelectionDAG.td
index 9c2e2c1a01b7b089f92885c5c741d8000e5d3d51..3856009bd29dd23a29143c63fa728bccb277d0cc 100644 (file)
--- a/lib/Target/TargetSelectionDAG.td
+++ b/lib/Target/TargetSelectionDAG.td
@@ -12,9 +12,6 @@
 //
 //===----------------------------------------------------------------------===//
 
-// Include all information about LLVM intrinsics.
-include "llvm/Intrinsics.td"
-
 //===----------------------------------------------------------------------===//
 // Selection DAG Type Constraint definitions.
 //
@@ -314,6 +311,18 @@ def build_vector : SDNode<"ISD::BUILD_VECTOR", SDTypeProfile<1, 0, []>, []>;
 def scalar_to_vector : SDNode<"ISD::SCALAR_TO_VECTOR", SDTypeProfile<1, 1, []>,
                               []>;
 
+// Nodes for intrinsics, you should use the intrinsic itself and let tblgen use
+// these internally.  Don't reference these directly.
+def intrinsic_void : SDNode<"ISD::INTRINSIC", 
+                            SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>,
+                            [SDNPHasChain]>;
+def intrinsic_w_chain : SDNode<"ISD::INTRINSIC", 
+                               SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>,
+                               [SDNPHasChain]>;
+def intrinsic_wo_chain : SDNode<"ISD::INTRINSIC", 
+                                SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>, []>;
+
+
 //===----------------------------------------------------------------------===//
 // Selection DAG Condition Codes