Removed the "inline" keyword from the disassembler decoder,

[oota-llvm.git] / lib / Target / X86 / Disassembler / X86Disassembler.cpp

diff --git a/lib/Target/X86/Disassembler/X86Disassembler.cpp b/lib/Target/X86/Disassembler/X86Disassembler.cpp
index 99617e7a40c9185681b86c2a7d5c3cccc7098e2f..a31686027a095c7fd254e8431079e37fdd769dfd 100644 (file)
--- a/lib/Target/X86/Disassembler/X86Disassembler.cpp
+++ b/lib/Target/X86/Disassembler/X86Disassembler.cpp
@@ -16,7 +16,6 @@
 
 #include "X86Disassembler.h"
 #include "X86DisassemblerDecoder.h"
-#include "X86InstrInfo.h"
 
 #include "llvm/MC/MCDisassembler.h"
 #include "llvm/MC/MCDisassembler.h"
@@ -25,6 +24,9 @@
 #include "llvm/Support/MemoryObject.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/raw_ostream.h"
+
+#include "X86GenRegisterNames.inc"
+
 using namespace llvm;
 using namespace llvm::X86Disassembler;
 
@@ -44,6 +46,8 @@ namespace X86 {
   };
 }
 
+extern Target TheX86_32Target, TheX86_64Target;
+
 }
 
 static void translateInstruction(MCInst &target,
@@ -179,8 +183,12 @@ static void translateRMRegister(MCInst &mcInst,
 /// @param mcInst       - The MCInst to append to.
 /// @param insn         - The instruction to extract Mod, R/M, and SIB fields
 ///                       from.
+/// @param sr           - Whether or not to emit the segment register.  The
+///                       LEA instruction does not expect a segment-register
+///                       operand.
 static void translateRMMemory(MCInst &mcInst,
-                              InternalInstruction &insn) {
+                              InternalInstruction &insn,
+                              bool sr) {
   // Addresses in an MCInst are represented as five operands:
   //   1. basereg       (register)  The R/M base, or (if there is a SIB) the 
   //                                SIB base
@@ -205,7 +213,7 @@ static void translateRMMemory(MCInst &mcInst,
       default:
         llvm_unreachable("Unexpected sibBase");
 #define ENTRY(x)                                          \
-      case SIB_BASE_##x:                                \
+      case SIB_BASE_##x:                                  \
         baseReg = MCOperand::CreateReg(X86::x); break;
       ALL_SIB_BASES
 #undef ENTRY
@@ -218,7 +226,7 @@ static void translateRMMemory(MCInst &mcInst,
       switch (insn.sibIndex) {
       default:
         llvm_unreachable("Unexpected sibIndex");
-#define ENTRY(x)                                            \
+#define ENTRY(x)                                          \
       case SIB_INDEX_##x:                                 \
         indexReg = MCOperand::CreateReg(X86::x); break;
       EA_BASES_32BIT
@@ -282,6 +290,8 @@ static void translateRMMemory(MCInst &mcInst,
             break;
       }
     }
+    
+    scaleAmount = MCOperand::CreateImm(1);
   }
   
   displacement = MCOperand::CreateImm(insn.displacement);
@@ -302,7 +312,9 @@ static void translateRMMemory(MCInst &mcInst,
   mcInst.addOperand(scaleAmount);
   mcInst.addOperand(indexReg);
   mcInst.addOperand(displacement);
-  mcInst.addOperand(segmentReg);
+  
+  if (sr)
+    mcInst.addOperand(segmentReg);
 }
 
 /// translateRM - Translates an operand stored in the R/M (and possibly SIB)
@@ -352,7 +364,10 @@ static void translateRM(MCInst &mcInst,
   case TYPE_M1616:
   case TYPE_M1632:
   case TYPE_M1664:
-    translateRMMemory(mcInst, insn);
+    translateRMMemory(mcInst, insn, true);
+    break;
+  case TYPE_LEA:
+    translateRMMemory(mcInst, insn, false);
     break;
   }
 }