#include "X86.h"
#include "X86InstrInfo.h"
+#include "X86InstrBuilder.h"
#include "llvm/Function.h"
#include "llvm/iTerminators.h"
#include "llvm/iOperators.h"
#include "llvm/iOther.h"
#include "llvm/iPHINode.h"
+#include "llvm/iMemory.h"
#include "llvm/Type.h"
#include "llvm/Constants.h"
#include "llvm/Pass.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/Target/TargetMachine.h"
#include "llvm/Support/InstVisitor.h"
+#include "llvm/Target/MRegisterInfo.h"
+#include <map>
+
+using namespace MOTy; // Get Use, Def, UseAndDef
namespace {
struct ISel : public FunctionPass, InstVisitor<ISel> {
F = &MachineFunction::construct(&Fn, TM);
visit(Fn);
RegMap.clear();
+ CurReg = MRegisterInfo::FirstVirtualRegister;
F = 0;
return false; // We never modify the LLVM itself.
}
// Visitation methods for various instructions. These methods simply emit
// fixed X86 code for each instruction.
//
+
+ // Control flow operators
void visitReturnInst(ReturnInst &RI);
void visitBranchInst(BranchInst &BI);
+ void visitCallInst(CallInst &I);
// Arithmetic operators
void visitSimpleBinary(BinaryOperator &B, unsigned OpcodeClass);
void visitXor(BinaryOperator &B) { visitSimpleBinary(B, 4); }
// Binary comparison operators
+ void visitSetCCInst(SetCondInst &I, unsigned OpNum);
+ void visitSetEQ(SetCondInst &I) { visitSetCCInst(I, 0); }
+ void visitSetNE(SetCondInst &I) { visitSetCCInst(I, 1); }
+ void visitSetLT(SetCondInst &I) { visitSetCCInst(I, 2); }
+ void visitSetGT(SetCondInst &I) { visitSetCCInst(I, 3); }
+ void visitSetLE(SetCondInst &I) { visitSetCCInst(I, 4); }
+ void visitSetGE(SetCondInst &I) { visitSetCCInst(I, 5); }
+
+ // Memory Instructions
+ void visitLoadInst(LoadInst &I);
+ void visitStoreInst(StoreInst &I);
// Other operators
void visitShiftInst(ShiftInst &I);
- void visitSetCondInst(SetCondInst &I);
void visitPHINode(PHINode &I);
+ void visitCastInst(CastInst &I);
void visitInstruction(Instruction &I) {
std::cerr << "Cannot instruction select: " << I;
abort();
}
+ void promote32 (const unsigned targetReg, Value *v);
/// copyConstantToRegister - Output the instructions required to put the
/// specified constant into the specified register.
unsigned getReg(Value &V) { return getReg(&V); } // Allow references
unsigned getReg(Value *V) {
unsigned &Reg = RegMap[V];
- if (Reg == 0)
+ if (Reg == 0) {
Reg = CurReg++;
+ RegMap[V] = Reg;
+
+ // Add the mapping of regnumber => reg class to MachineFunction
+ F->addRegMap(Reg,
+ TM.getRegisterInfo()->getRegClassForType(V->getType()));
+ }
// If this operand is a constant, emit the code to copy the constant into
// the register here...
//
- if (Constant *C = dyn_cast<Constant>(V))
+ if (Constant *C = dyn_cast<Constant>(V)) {
copyConstantToRegister(C, Reg);
+ } else if (GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
+ // Move the address of the global into the register
+ BuildMI(BB, X86::MOVir32, 1, Reg).addReg(GV);
+ } else if (Argument *A = dyn_cast<Argument>(V)) {
+ std::cerr << "ERROR: Arguments not implemented in SimpleInstSel\n";
+ }
return Reg;
}
}
}
+
/// copyConstantToRegister - Output the instructions required to put the
/// specified constant into the specified register.
///
}
}
+
/// SetCC instructions - Here we just emit boilerplate code to set a byte-sized
/// register, then move it to wherever the result should be.
/// We handle FP setcc instructions by pushing them, doing a
/// compare-and-pop-twice, and then copying the concodes to the main
/// processor's concodes (I didn't make this up, it's in the Intel manual)
///
-void
-ISel::visitSetCondInst (SetCondInst & I)
-{
+void ISel::visitSetCCInst(SetCondInst &I, unsigned OpNum) {
// The arguments are already supposed to be of the same type.
- Value *var1 = I.getOperand (0);
- Value *var2 = I.getOperand (1);
- unsigned reg1 = getReg (var1);
- unsigned reg2 = getReg (var2);
- unsigned resultReg = getReg (I);
- unsigned comparisonWidth = var1->getType ()->getPrimitiveSize ();
- unsigned unsignedComparison = var1->getType ()->isUnsigned ();
- unsigned resultWidth = I.getType ()->getPrimitiveSize ();
- bool fpComparison = var1->getType ()->isFloatingPoint ();
- if (fpComparison)
- {
- // Push the variables on the stack with fldl opcodes.
- // FIXME: assuming var1, var2 are in memory, if not, spill to
- // stack first
- switch (comparisonWidth)
- {
- case 4:
- BuildMI (BB, X86::FLDr4, 1, X86::NoReg).addReg (reg1);
- break;
- case 8:
- BuildMI (BB, X86::FLDr8, 1, X86::NoReg).addReg (reg1);
- break;
- default:
- visitInstruction (I);
- break;
- }
- switch (comparisonWidth)
- {
- case 4:
- BuildMI (BB, X86::FLDr4, 1, X86::NoReg).addReg (reg2);
- break;
- case 8:
- BuildMI (BB, X86::FLDr8, 1, X86::NoReg).addReg (reg2);
- break;
- default:
- visitInstruction (I);
- break;
- }
- // (Non-trapping) compare and pop twice.
- BuildMI (BB, X86::FUCOMPP, 0);
- // Move fp status word (concodes) to ax.
- BuildMI (BB, X86::FNSTSWr8, 1, X86::AX);
- // Load real concodes from ax.
- BuildMI (BB, X86::SAHF, 1, X86::EFLAGS).addReg(X86::AH);
- }
- else
- { // integer comparison
- // Emit: cmp <var1>, <var2> (do the comparison). We can
- // compare 8-bit with 8-bit, 16-bit with 16-bit, 32-bit with
- // 32-bit.
- switch (comparisonWidth)
- {
- case 1:
- BuildMI (BB, X86::CMPrr8, 2,
- X86::EFLAGS).addReg (reg1).addReg (reg2);
- break;
- case 2:
- BuildMI (BB, X86::CMPrr16, 2,
- X86::EFLAGS).addReg (reg1).addReg (reg2);
- break;
- case 4:
- BuildMI (BB, X86::CMPrr32, 2,
- X86::EFLAGS).addReg (reg1).addReg (reg2);
- break;
- case 8:
- default:
- visitInstruction (I);
- break;
- }
- }
+ const Type *CompTy = I.getOperand(0)->getType();
+ unsigned reg1 = getReg(I.getOperand(0));
+ unsigned reg2 = getReg(I.getOperand(1));
+
+ unsigned Class = getClass(CompTy);
+ switch (Class) {
+ // Emit: cmp <var1>, <var2> (do the comparison). We can
+ // compare 8-bit with 8-bit, 16-bit with 16-bit, 32-bit with
+ // 32-bit.
+ case cByte:
+ BuildMI (BB, X86::CMPrr8, 2).addReg (reg1).addReg (reg2);
+ break;
+ case cShort:
+ BuildMI (BB, X86::CMPrr16, 2).addReg (reg1).addReg (reg2);
+ break;
+ case cInt:
+ BuildMI (BB, X86::CMPrr32, 2).addReg (reg1).addReg (reg2);
+ break;
+
+ // Push the variables on the stack with fldl opcodes.
+ // FIXME: assuming var1, var2 are in memory, if not, spill to
+ // stack first
+ case cFloat: // Floats
+ BuildMI (BB, X86::FLDr4, 1).addReg (reg1);
+ BuildMI (BB, X86::FLDr4, 1).addReg (reg2);
+ break;
+ case cDouble: // Doubles
+ BuildMI (BB, X86::FLDr8, 1).addReg (reg1);
+ BuildMI (BB, X86::FLDr8, 1).addReg (reg2);
+ break;
+ case cLong:
+ default:
+ visitInstruction(I);
+ }
+
+ if (CompTy->isFloatingPoint()) {
+ // (Non-trapping) compare and pop twice.
+ BuildMI (BB, X86::FUCOMPP, 0);
+ // Move fp status word (concodes) to ax.
+ BuildMI (BB, X86::FNSTSWr8, 1, X86::AX);
+ // Load real concodes from ax.
+ BuildMI (BB, X86::SAHF, 1).addReg(X86::AH);
+ }
+
// Emit setOp instruction (extract concode; clobbers ax),
// using the following mapping:
// LLVM -> X86 signed X86 unsigned
// setgt -> setg seta
// setle -> setle setbe
// setge -> setge setae
- switch (I.getOpcode ())
- {
- case Instruction::SetEQ:
- BuildMI (BB, X86::SETE, 0, X86::AL);
- break;
- case Instruction::SetGE:
- if (unsignedComparison)
- BuildMI (BB, X86::SETAE, 0, X86::AL);
- else
- BuildMI (BB, X86::SETGE, 0, X86::AL);
- break;
- case Instruction::SetGT:
- if (unsignedComparison)
- BuildMI (BB, X86::SETA, 0, X86::AL);
- else
- BuildMI (BB, X86::SETG, 0, X86::AL);
- break;
- case Instruction::SetLE:
- if (unsignedComparison)
- BuildMI (BB, X86::SETBE, 0, X86::AL);
- else
- BuildMI (BB, X86::SETLE, 0, X86::AL);
- break;
- case Instruction::SetLT:
- if (unsignedComparison)
- BuildMI (BB, X86::SETB, 0, X86::AL);
- else
- BuildMI (BB, X86::SETL, 0, X86::AL);
- break;
- case Instruction::SetNE:
- BuildMI (BB, X86::SETNE, 0, X86::AL);
- break;
- default:
- visitInstruction (I);
- break;
- }
+
+ static const unsigned OpcodeTab[2][6] = {
+ {X86::SETEr, X86::SETNEr, X86::SETBr, X86::SETAr, X86::SETBEr, X86::SETAEr},
+ {X86::SETEr, X86::SETNEr, X86::SETLr, X86::SETGr, X86::SETLEr, X86::SETGEr},
+ };
+
+ BuildMI(BB, OpcodeTab[CompTy->isSigned()][OpNum], 0, X86::AL);
+
// Put it in the result using a move.
- switch (resultWidth)
+ BuildMI (BB, X86::MOVrr8, 1, getReg(I)).addReg(X86::AL);
+}
+
+/// promote32 - Emit instructions to turn a narrow operand into a 32-bit-wide
+/// operand, in the specified target register.
+void
+ISel::promote32 (const unsigned targetReg, Value *v)
+{
+ unsigned vReg = getReg (v);
+ unsigned Class = getClass (v->getType ());
+ bool isUnsigned = v->getType ()->isUnsigned ();
+ assert (((Class == cByte) || (Class == cShort) || (Class == cInt))
+ && "Unpromotable operand class in promote32");
+ switch (Class)
{
- case 1:
- BuildMI (BB, X86::MOVrr8, 1, resultReg).addReg (X86::AL);
- break;
- case 2:
- BuildMI (BB, X86::MOVZXr16r8, 1, resultReg).addReg (X86::AL);
+ case cByte:
+ // Extend value into target register (8->32)
+ if (isUnsigned)
+ BuildMI (BB, X86::MOVZXr32r8, 1, targetReg).addReg (vReg);
+ else
+ BuildMI (BB, X86::MOVSXr32r8, 1, targetReg).addReg (vReg);
break;
- case 4:
- BuildMI (BB, X86::MOVZXr32r8, 1, resultReg).addReg (X86::AL);
+ case cShort:
+ // Extend value into target register (16->32)
+ if (isUnsigned)
+ BuildMI (BB, X86::MOVZXr32r16, 1, targetReg).addReg (vReg);
+ else
+ BuildMI (BB, X86::MOVSXr32r16, 1, targetReg).addReg (vReg);
break;
- case 8:
- default:
- visitInstruction (I);
+ case cInt:
+ // Move value into target register (32->32)
+ BuildMI (BB, X86::MOVrr32, 1, targetReg).addReg (vReg);
break;
}
}
-
/// 'ret' instruction - Here we are interested in meeting the x86 ABI. As such,
/// we have the following possibilities:
///
/// ret short, ushort: Extend value into EAX and return
/// ret int, uint : Move value into EAX and return
/// ret pointer : Move value into EAX and return
-/// ret long, ulong : Move value into EAX/EDX (?) and return
-/// ret float/double : ? Top of FP stack? XMM0?
+/// ret long, ulong : Move value into EAX/EDX and return
+/// ret float/double : Top of FP stack
///
-void ISel::visitReturnInst (ReturnInst & I) {
- if (I.getNumOperands() == 0) {
- // Emit a 'ret' instruction
- BuildMI(BB, X86::RET, 0);
- return;
- }
-
- unsigned val = getReg(I.getOperand(0));
- unsigned Class = getClass(I.getType());
- bool isUnsigned = I.getOperand(0)->getType()->isUnsigned();
- switch (Class) {
- case cByte:
- // ret sbyte, ubyte: Extend value into EAX and return
- if (isUnsigned) {
- BuildMI (BB, X86::MOVZXr32r8, 1, X86::EAX).addReg (val);
- } else {
- BuildMI (BB, X86::MOVSXr32r8, 1, X86::EAX).addReg (val);
+void
+ISel::visitReturnInst (ReturnInst &I)
+{
+ if (I.getNumOperands () == 0)
+ {
+ // Emit a 'ret' instruction
+ BuildMI (BB, X86::RET, 0);
+ return;
}
- break;
- case cShort:
- // ret short, ushort: Extend value into EAX and return
- if (unsignedReturnValue) {
- BuildMI (BB, X86::MOVZXr32r16, 1, X86::EAX).addReg (val);
- } else {
- BuildMI (BB, X86::MOVSXr32r16, 1, X86::EAX).addReg (val);
+ Value *rv = I.getOperand (0);
+ unsigned Class = getClass (rv->getType ());
+ switch (Class)
+ {
+ // integral return values: extend or move into EAX and return.
+ case cByte:
+ case cShort:
+ case cInt:
+ promote32 (X86::EAX, rv);
+ break;
+ // ret float/double: top of FP stack
+ // FLD <val>
+ case cFloat: // Floats
+ BuildMI (BB, X86::FLDr4, 1).addReg (getReg (rv));
+ break;
+ case cDouble: // Doubles
+ BuildMI (BB, X86::FLDr8, 1).addReg (getReg (rv));
+ break;
+ case cLong:
+ // ret long: use EAX(least significant 32 bits)/EDX (most
+ // significant 32)...uh, I think so Brain, but how do i call
+ // up the two parts of the value from inside this mouse
+ // cage? *zort*
+ default:
+ visitInstruction (I);
}
- break;
- case cInt:
- // ret int, uint, ptr: Move value into EAX and return
- // MOV EAX, <val>
- BuildMI(BB, X86::MOVrr32, 1, X86::EAX).addReg(val);
- break;
-
- // ret float/double: top of FP stack
- // FLD <val>
- case cFloat: // Floats
- BuildMI(BB, X86::FLDr4, 1).addReg(val);
- break;
- case cDouble: // Doubles
- BuildMI(BB, X86::FLDr8, 1).addReg(val);
- break;
- case cLong:
- // ret long: use EAX(least significant 32 bits)/EDX (most
- // significant 32)...uh, I think so Brain, but how do i call
- // up the two parts of the value from inside this mouse
- // cage? *zort*
- default:
- visitInstruction(I);
- }
-
// Emit a 'ret' instruction
- BuildMI(BB, X86::RET, 0);
+ BuildMI (BB, X86::RET, 0);
}
/// visitBranchInst - Handle conditional and unconditional branches here. Note
/// jump to a block that is the immediate successor of the current block, we can
/// just make a fall-through. (but we don't currently).
///
-void ISel::visitBranchInst(BranchInst &BI) {
- if (BI.isConditional()) // Only handles unconditional branches so far...
- visitInstruction(BI);
-
- BuildMI(BB, X86::JMP, 1).addPCDisp(BI.getSuccessor(0));
+void
+ISel::visitBranchInst (BranchInst & BI)
+{
+ if (BI.isConditional ())
+ {
+ BasicBlock *ifTrue = BI.getSuccessor (0);
+ BasicBlock *ifFalse = BI.getSuccessor (1); // this is really unobvious
+
+ // simplest thing I can think of: compare condition with zero,
+ // followed by jump-if-equal to ifFalse, and jump-if-nonequal to
+ // ifTrue
+ unsigned int condReg = getReg (BI.getCondition ());
+ BuildMI (BB, X86::CMPri8, 2).addReg (condReg).addZImm (0);
+ BuildMI (BB, X86::JNE, 1).addPCDisp (BI.getSuccessor (0));
+ BuildMI (BB, X86::JE, 1).addPCDisp (BI.getSuccessor (1));
+ }
+ else // unconditional branch
+ {
+ BuildMI (BB, X86::JMP, 1).addPCDisp (BI.getSuccessor (0));
+ }
}
+/// visitCallInst - Push args on stack and do a procedure call instruction.
+void
+ISel::visitCallInst (CallInst & CI)
+{
+ // keep a counter of how many bytes we pushed on the stack
+ unsigned bytesPushed = 0;
+
+ // Push the arguments on the stack in reverse order, as specified by
+ // the ABI.
+ for (unsigned i = CI.getNumOperands()-1; i >= 1; --i)
+ {
+ Value *v = CI.getOperand (i);
+ switch (getClass (v->getType ()))
+ {
+ case cByte:
+ case cShort:
+ // Promote V to 32 bits wide, and move the result into EAX,
+ // then push EAX.
+ promote32 (X86::EAX, v);
+ BuildMI (BB, X86::PUSHr32, 1).addReg (X86::EAX);
+ bytesPushed += 4;
+ break;
+ case cInt:
+ case cFloat: {
+ unsigned Reg = getReg(v);
+ BuildMI (BB, X86::PUSHr32, 1).addReg(Reg);
+ bytesPushed += 4;
+ break;
+ }
+ default:
+ // FIXME: long/ulong/double args not handled.
+ visitInstruction (CI);
+ break;
+ }
+ }
+ // Emit a CALL instruction with PC-relative displacement.
+ BuildMI (BB, X86::CALLpcrel32, 1).addPCDisp (CI.getCalledValue ());
+
+ // Adjust the stack by `bytesPushed' amount if non-zero
+ if (bytesPushed > 0)
+ BuildMI (BB, X86::ADDri32, 2).addReg(X86::ESP).addZImm(bytesPushed);
+
+ // If there is a return value, scavenge the result from the location the call
+ // leaves it in...
+ //
+ if (CI.getType() != Type::VoidTy) {
+ switch (getClass(CI.getType())) {
+ case cInt:
+ BuildMI(BB, X86::MOVrr32, 1, getReg(CI)).addReg(X86::EAX);
+ break;
+
+ default:
+ std::cerr << "Cannot get return value for call of type '"
+ << *CI.getType() << "'\n";
+ visitInstruction(CI);
+ }
+ }
+}
/// visitSimpleBinary - Implement simple binary operators for integral types...
/// OperatorClass is one of: 0 for Add, 1 for Sub, 2 for And, 3 for Or,
static const unsigned MulOpcode[]={ X86::MULrr8, X86::MULrr16, X86::MULrr32 };
static const unsigned MovOpcode[]={ X86::MOVrr8, X86::MOVrr16, X86::MOVrr32 };
- unsigned Reg = Regs[Class];
- unsigned Op0Reg = getReg(I.getOperand(1));
- unsigned Op1Reg = getReg(I.getOperand(1));
+ unsigned Reg = Regs[Class];
+ unsigned Op0Reg = getReg(I.getOperand(0));
+ unsigned Op1Reg = getReg(I.getOperand(1));
// Put the first operand into one of the A registers...
BuildMI(BB, MovOpcode[Class], 1, Reg).addReg(Op0Reg);
- // Emit the appropriate multiple instruction...
- // FIXME: We need to mark that this modified AH, DX, or EDX also!!
- BuildMI(BB, MulOpcode[Class], 2, Reg).addReg(Reg).addReg(Op1Reg);
+ // Emit the appropriate multiply instruction...
+ BuildMI(BB, MulOpcode[Class], 1).addReg(Op1Reg);
// Put the result into the destination register...
BuildMI(BB, MovOpcode[Class], 1, getReg(I)).addReg(Reg);
}
+
/// visitDivRem - Handle division and remainder instructions... these
/// instruction both require the same instructions to be generated, they just
/// select the result from a different register. Note that both of these
bool isSigned = I.getType()->isSigned();
unsigned Reg = Regs[Class];
unsigned ExtReg = ExtRegs[Class];
- unsigned Op0Reg = getReg(I.getOperand(1));
+ unsigned Op0Reg = getReg(I.getOperand(0));
unsigned Op1Reg = getReg(I.getOperand(1));
// Put the first operand into one of the A registers...
if (isSigned) {
// Emit a sign extension instruction...
- BuildMI(BB, ExtOpcode[Class], 1, ExtReg).addReg(Reg);
+ BuildMI(BB, ExtOpcode[Class], 0);
} else {
// If unsigned, emit a zeroing instruction... (reg = xor reg, reg)
BuildMI(BB, ClrOpcode[Class], 2, ExtReg).addReg(ExtReg).addReg(ExtReg);
}
+ // Emit the appropriate divide or remainder instruction...
+ BuildMI(BB, DivOpcode[isSigned][Class], 1).addReg(Op1Reg);
+
// Figure out which register we want to pick the result out of...
unsigned DestReg = (I.getOpcode() == Instruction::Div) ? Reg : ExtReg;
- // Emit the appropriate divide or remainder instruction...
- // FIXME: We need to mark that this modified AH, DX, or EDX also!!
- BuildMI(BB,DivOpcode[isSigned][Class], 2, DestReg).addReg(Reg).addReg(Op1Reg);
-
// Put the result into the destination register...
BuildMI(BB, MovOpcode[Class], 1, getReg(I)).addReg(DestReg);
}
+
/// Shift instructions: 'shl', 'sar', 'shr' - Some special cases here
/// for constant immediate shift values, and for constant immediate
/// shift values equal to 1. Even the general case is sort of special,
const unsigned *OpTab = // Figure out the operand table to use
NonConstantOperand[isLeftShift*2+isOperandSigned];
- BuildMI(BB, OpTab[OperandClass], 2, DestReg).addReg(Op0r).addReg(X86::CL);
+ BuildMI(BB, OpTab[OperandClass], 1, DestReg).addReg(Op0r);
}
}
+
+/// visitLoadInst - Implement LLVM load instructions in terms of the x86 'mov'
+/// instruction.
+///
+void ISel::visitLoadInst(LoadInst &I) {
+ unsigned Class = getClass(I.getType());
+ if (Class > 2) // FIXME: Handle longs and others...
+ visitInstruction(I);
+
+ static const unsigned Opcode[] = { X86::MOVmr8, X86::MOVmr16, X86::MOVmr32 };
+
+ unsigned AddressReg = getReg(I.getOperand(0));
+ addDirectMem(BuildMI(BB, Opcode[Class], 4, getReg(I)), AddressReg);
+}
+
+
+/// visitStoreInst - Implement LLVM store instructions in terms of the x86 'mov'
+/// instruction.
+///
+void ISel::visitStoreInst(StoreInst &I) {
+ unsigned Class = getClass(I.getOperand(0)->getType());
+ if (Class > 2) // FIXME: Handle longs and others...
+ visitInstruction(I);
+
+ static const unsigned Opcode[] = { X86::MOVrm8, X86::MOVrm16, X86::MOVrm32 };
+
+ unsigned ValReg = getReg(I.getOperand(0));
+ unsigned AddressReg = getReg(I.getOperand(1));
+ addDirectMem(BuildMI(BB, Opcode[Class], 1+4), AddressReg).addReg(ValReg);
+}
+
+
/// visitPHINode - Turn an LLVM PHI node into an X86 PHI node...
///
void ISel::visitPHINode(PHINode &PN) {
}
}
+/// visitCastInst - Here we have various kinds of copying with or without
+/// sign extension going on.
+void
+ISel::visitCastInst (CastInst &CI)
+{
+ const Type *targetType = CI.getType ();
+ Value *operand = CI.getOperand (0);
+ unsigned int operandReg = getReg (operand);
+ const Type *sourceType = operand->getType ();
+ unsigned int destReg = getReg (CI);
+ //
+ // Currently we handle:
+ //
+ // 1) cast * to bool
+ //
+ // 2) cast {sbyte, ubyte} to {sbyte, ubyte}
+ // cast {short, ushort} to {ushort, short}
+ // cast {int, uint, ptr} to {int, uint, ptr}
+ //
+ // 3) cast {sbyte, ubyte} to {ushort, short}
+ // cast {sbyte, ubyte} to {int, uint, ptr}
+ // cast {short, ushort} to {int, uint, ptr}
+ //
+ // 4) cast {int, uint, ptr} to {short, ushort}
+ // cast {int, uint, ptr} to {sbyte, ubyte}
+ // cast {short, ushort} to {sbyte, ubyte}
+ //
+ // 1) Implement casts to bool by using compare on the operand followed
+ // by set if not zero on the result.
+ if (targetType == Type::BoolTy)
+ {
+ BuildMI (BB, X86::CMPri8, 2).addReg (operandReg).addZImm (0);
+ BuildMI (BB, X86::SETNEr, 1, destReg);
+ return;
+ }
+ // 2) Implement casts between values of the same type class (as determined
+ // by getClass) by using a register-to-register move.
+ unsigned int srcClass = getClass (sourceType);
+ unsigned int targClass = getClass (targetType);
+ static const unsigned regRegMove[] = {
+ X86::MOVrr8, X86::MOVrr16, X86::MOVrr32
+ };
+ if ((srcClass < 3) && (targClass < 3) && (srcClass == targClass))
+ {
+ BuildMI (BB, regRegMove[srcClass], 1, destReg).addReg (operandReg);
+ return;
+ }
+ // 3) Handle cast of SMALLER int to LARGER int using a move with sign
+ // extension or zero extension, depending on whether the source type
+ // was signed.
+ if ((srcClass < 3) && (targClass < 3) && (srcClass < targClass))
+ {
+ static const unsigned ops[] = {
+ X86::MOVSXr16r8, X86::MOVSXr32r8, X86::MOVSXr32r16,
+ X86::MOVZXr16r8, X86::MOVZXr32r8, X86::MOVZXr32r16
+ };
+ unsigned srcSigned = sourceType->isSigned ();
+ BuildMI (BB, ops[3 * srcSigned + srcClass + targClass - 1], 1,
+ destReg).addReg (operandReg);
+ return;
+ }
+ // 4) Handle cast of LARGER int to SMALLER int using a move to EAX
+ // followed by a move out of AX or AL.
+ if ((srcClass < 3) && (targClass < 3) && (srcClass > targClass))
+ {
+ static const unsigned AReg[] = { X86::AL, X86::AX, X86::EAX };
+ BuildMI (BB, regRegMove[srcClass], 1,
+ AReg[srcClass]).addReg (operandReg);
+ BuildMI (BB, regRegMove[targClass], 1, destReg).addReg (AReg[srcClass]);
+ return;
+ }
+ // Anything we haven't handled already, we can't (yet) handle at all.
+ visitInstruction (CI);
+}
/// createSimpleX86InstructionSelector - This pass converts an LLVM function
/// into a machine code representation is a very simple peep-hole fashion. The
projects / oota-llvm.git / blobdiff