Fix the last crimes against nature that used the 'ir' ordering to use the

[oota-llvm.git] / lib / Target / X86 / Makefile

diff --git a/lib/Target/X86/Makefile b/lib/Target/X86/Makefile
index 25aa728ca7162c2dac52c62dc4627bfe3349639a..b151fa7ecf71d9b8c4f431eb64b3b0fdd92fe711 100644 (file)
--- a/lib/Target/X86/Makefile
+++ b/lib/Target/X86/Makefile
@@ -1,3 +1,11 @@
+##===- lib/Target/X86/Makefile -----------------------------*- Makefile -*-===##
+# 
+#                     The LLVM Compiler Infrastructure
+#
+# This file was developed by the LLVM research group and is distributed under
+# the University of Illinois Open Source License. See LICENSE.TXT for details.
+# 
+##===----------------------------------------------------------------------===##
 LEVEL = ../../..
 LIBRARYNAME = x86
 include $(LEVEL)/Makefile.common
@@ -7,24 +15,35 @@ $(SourceDepend): X86GenRegisterInfo.h.inc X86GenRegisterNames.inc \
                  X86GenRegisterInfo.inc X86GenInstrNames.inc \
                  X86GenInstrInfo.inc X86GenInstrSelector.inc
 
-X86GenRegisterNames.inc:  X86.td X86RegisterInfo.td ../Target.td $(TBLGEN)
-       $(TBLGEN) $< -gen-register-enums -o $@
+X86GenRegisterNames.inc::  $(SourceDir)/X86.td $(SourceDir)/X86RegisterInfo.td \
+                           $(SourceDir)/../Target.td $(TBLGEN)
+       @echo "Building X86.td register names with tblgen"
+       $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-enums -o $@
 
-X86GenRegisterInfo.h.inc: X86.td X86RegisterInfo.td ../Target.td $(TBLGEN)
-       $(TBLGEN) $< -gen-register-desc-header -o $@
+X86GenRegisterInfo.h.inc:: $(SourceDir)/X86.td $(SourceDir)/X86RegisterInfo.td \
+                           $(SourceDir)/../Target.td $(TBLGEN)
+       @echo "Building X86.td register information header with tblgen"
+       $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-desc-header -o $@
 
-X86GenRegisterInfo.inc: X86.td X86RegisterInfo.td ../Target.td $(TBLGEN)
-       $(TBLGEN) $< -gen-register-desc -o $@
+X86GenRegisterInfo.inc:: $(SourceDir)/X86.td $(SourceDir)/X86RegisterInfo.td \
+                         $(SourceDir)/../Target.td $(TBLGEN)
+       @echo "Building X86.td register information implementation with tblgen"
+       $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-desc -o $@
 
-X86GenInstrNames.inc: X86.td X86InstrInfo.td ../Target.td $(TBLGEN)
-       $(TBLGEN) $< -gen-instr-enums -o $@
+X86GenInstrNames.inc:: $(SourceDir)/X86.td $(SourceDir)/X86InstrInfo.td \
+                       $(SourceDir)/../Target.td $(TBLGEN)
+       @echo "Building X86.td instruction names with tblgen"
+       $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-enums -o $@
 
-X86GenInstrInfo.inc: X86.td X86InstrInfo.td ../Target.td $(TBLGEN)
-       $(TBLGEN) $< -gen-instr-desc -o $@
+X86GenInstrInfo.inc:: $(SourceDir)/X86.td $(SourceDir)/X86InstrInfo.td \
+                      $(SourceDir)/../Target.td $(TBLGEN)
+       @echo "Building X86.td instruction information with tblgen"
+       $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-desc -o $@
 
-X86GenInstrSelector.inc: X86.td X86InstrInfo.td ../Target.td $(TBLGEN)
-       $(TBLGEN) $< -debug -gen-instr-selector -o $@
+X86GenInstrSelector.inc:: $(SourceDir)/X86.td $(SourceDir)/X86InstrInfo.td \
+                          $(SourceDir)/../Target.td $(TBLGEN)
+       @echo "Building X86.td instruction selector with tblgen"
+       $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-selector -o $@
 
 clean::
        $(VERB) rm -f *.inc
-