#include "Support/Statistic.h"
#include "Support/StringExtras.h"
#include "Support/CommandLine.h"
-
-namespace llvm {
+using namespace llvm;
namespace {
Statistic<> EmittedInsts("asm-printer", "Number of machine instrs printed");
/// using the given target machine description. This should work
/// regardless of whether the function is in SSA form.
///
-FunctionPass *createX86CodePrinterPass(std::ostream &o,TargetMachine &tm){
+FunctionPass *llvm::createX86CodePrinterPass(std::ostream &o,TargetMachine &tm){
return new Printer(o, tm);
}
-/// isStringCompatible - Can we treat the specified array as a string?
-/// Only if it is an array of ubytes or non-negative sbytes.
-///
-static bool isStringCompatible(const ConstantArray *CVA) {
- const Type *ETy = cast<ArrayType>(CVA->getType())->getElementType();
- if (ETy == Type::UByteTy) return true;
- if (ETy != Type::SByteTy) return false;
-
- for (unsigned i = 0; i < CVA->getNumOperands(); ++i)
- if (cast<ConstantSInt>(CVA->getOperand(i))->getValue() < 0)
- return false;
-
- return true;
-}
-
/// toOctal - Convert the low order bits of X into an octal digit.
///
static inline char toOctal(int X) {
/// string, only if the predicate isStringCompatible is true.
///
static void printAsCString(std::ostream &O, const ConstantArray *CVA) {
- assert(isStringCompatible(CVA) && "Array is not string compatible!");
+ assert(CVA->isString() && "Array is not string compatible!");
O << "\"";
- for (unsigned i = 0; i < CVA->getNumOperands(); ++i) {
+ for (unsigned i = 0; i != CVA->getNumOperands(); ++i) {
unsigned char C = cast<ConstantInt>(CVA->getOperand(i))->getRawValue();
if (C == '"') {
assert(CB == ConstantBool::True);
O << "1";
} else if (const ConstantSInt *CI = dyn_cast<ConstantSInt>(CV))
- O << CI->getValue();
+ if (((CI->getValue() << 32) >> 32) == CI->getValue())
+ O << CI->getValue();
+ else
+ O << (unsigned long long)CI->getValue();
else if (const ConstantUInt *CI = dyn_cast<ConstantUInt>(CV))
O << CI->getValue();
else if (const ConstantPointerRef *CPR = dyn_cast<ConstantPointerRef>(CV))
O << "\t.zero\t " << TD.getTypeSize(CV->getType()) << "\n";
return;
} else if (const ConstantArray *CVA = dyn_cast<ConstantArray>(CV)) {
- if (isStringCompatible(CVA)) {
+ if (CVA->isString()) {
O << "\t.ascii\t";
printAsCString(O, CVA);
O << "\n";
II != E; ++II) {
// Print the assembly for the instruction.
O << "\t";
- printMachineInstruction(*II);
+ printMachineInstruction(II);
}
}
}
// FALLTHROUGH
case MachineOperand::MO_MachineRegister:
- if (MO.getReg() < MRegisterInfo::FirstVirtualRegister)
+ if (MRegisterInfo::isPhysicalRegister(MO.getReg()))
// Bug Workaround: See note in Printer::doInitialization about %.
O << "%" << RI.get(MO.getReg()).Name;
else
}
}
-static const std::string sizePtr(const TargetInstrDescriptor &Desc) {
- switch (Desc.TSFlags & X86II::ArgMask) {
+static const char* const sizePtr(const TargetInstrDescriptor &Desc) {
+ switch (Desc.TSFlags & X86II::MemMask) {
default: assert(0 && "Unknown arg size!");
- case X86II::Arg8: return "BYTE PTR";
- case X86II::Arg16: return "WORD PTR";
- case X86II::Arg32: return "DWORD PTR";
- case X86II::Arg64: return "QWORD PTR";
- case X86II::ArgF32: return "DWORD PTR";
- case X86II::ArgF64: return "QWORD PTR";
- case X86II::ArgF80: return "XWORD PTR";
+ case X86II::Mem8: return "BYTE PTR";
+ case X86II::Mem16: return "WORD PTR";
+ case X86II::Mem32: return "DWORD PTR";
+ case X86II::Mem64: return "QWORD PTR";
+ case X86II::Mem80: return "XWORD PTR";
}
}
}
} else {
unsigned i = 0;
- if (MI->getNumOperands() && (MI->getOperand(0).opIsDefOnly() ||
- MI->getOperand(0).opIsDefAndUse())) {
+ if (MI->getNumOperands() && MI->getOperand(0).isDef()) {
printOp(MI->getOperand(0));
O << " = ";
++i;
for (unsigned e = MI->getNumOperands(); i != e; ++i) {
O << " ";
- if (MI->getOperand(i).opIsDefOnly() ||
- MI->getOperand(i).opIsDefAndUse()) O << "*";
+ if (MI->getOperand(i).isDef()) O << "*";
printOp(MI->getOperand(i));
- if (MI->getOperand(i).opIsDefOnly() ||
- MI->getOperand(i).opIsDefAndUse()) O << "*";
+ if (MI->getOperand(i).isDef()) O << "*";
}
}
O << "\n";
unsigned Reg = MI->getOperand(0).getReg();
- O << TII.getName(MI->getOpCode()) << " ";
+ O << TII.getName(MI->getOpcode()) << " ";
printOp(MI->getOperand(0));
if (MI->getNumOperands() == 2 &&
(!MI->getOperand(1).isRegister() ||
return;
}
case X86II::MRMDestReg: {
- // There are two acceptable forms of MRMDestReg instructions, those with 2,
- // 3 and 4 operands:
+ // There are three forms of MRMDestReg instructions, those with 2
+ // or 3 operands:
//
- // 2 Operands: this is for things like mov that do not read a second input
+ // 2 Operands: this is for things like mov that do not read a
+ // second input.
//
- // 3 Operands: in this form, the first two registers (the destination, and
- // the first operand) should be the same, post register allocation. The 3rd
- // operand is an additional input. This should be for things like add
- // instructions.
+ // 2 Operands: two address instructions which def&use the first
+ // argument and use the second as input.
//
- // 4 Operands: This form is for instructions which are 3 operands forms, but
- // have a constant argument as well.
+ // 3 Operands: in this form, two address instructions are the same
+ // as in 2 but have a constant argument as well.
//
bool isTwoAddr = TII.isTwoAddrInstr(Opcode);
assert(MI->getOperand(0).isRegister() &&
(MI->getNumOperands() == 2 ||
- (isTwoAddr && MI->getOperand(1).isRegister() &&
- MI->getOperand(0).getReg() == MI->getOperand(1).getReg() &&
- (MI->getNumOperands() == 3 ||
- (MI->getNumOperands() == 4 && MI->getOperand(3).isImmediate()))))
+ (MI->getNumOperands() == 3 && MI->getOperand(2).isImmediate()))
&& "Bad format for MRMDestReg!");
- O << TII.getName(MI->getOpCode()) << " ";
+ O << TII.getName(MI->getOpcode()) << " ";
printOp(MI->getOperand(0));
O << ", ";
- printOp(MI->getOperand(1+isTwoAddr));
- if (MI->getNumOperands() == 4) {
+ printOp(MI->getOperand(1));
+ if (MI->getNumOperands() == 3) {
O << ", ";
- printOp(MI->getOperand(3));
+ printOp(MI->getOperand(2));
}
O << "\n";
return;
// These instructions are the same as MRMDestReg, but instead of having a
// register reference for the mod/rm field, it's a memory reference.
//
- assert(isMem(MI, 0) && MI->getNumOperands() == 4+1 &&
- MI->getOperand(4).isRegister() && "Bad format for MRMDestMem!");
+ assert(isMem(MI, 0) &&
+ (MI->getNumOperands() == 4+1 ||
+ (MI->getNumOperands() == 4+2 && MI->getOperand(5).isImmediate()))
+ && "Bad format for MRMDestMem!");
- O << TII.getName(MI->getOpCode()) << " " << sizePtr(Desc) << " ";
+ O << TII.getName(MI->getOpcode()) << " " << sizePtr(Desc) << " ";
printMemReference(MI, 0);
O << ", ";
printOp(MI->getOperand(4));
+ if (MI->getNumOperands() == 4+2) {
+ O << ", ";
+ printOp(MI->getOperand(5));
+ }
O << "\n";
return;
}
case X86II::MRMSrcReg: {
- // There are three forms that are acceptable for MRMSrcReg instructions,
- // those with 3 and 2 operands:
+ // There are three forms that are acceptable for MRMSrcReg
+ // instructions, those with 2 or 3 operands:
+ //
+ // 2 Operands: this is for things like mov that do not read a
+ // second input.
//
- // 3 Operands: in this form, the last register (the second input) is the
- // ModR/M input. The first two operands should be the same, post register
- // allocation. This is for things like: add r32, r/m32
+ // 2 Operands: in this form, the last register is the ModR/M
+ // input. The first operand is a def&use. This is for things
+ // like: add r32, r/m32
//
- // 3 Operands: in this form, we can have 'INST R, R, imm', which is used for
- // instructions like the IMULri instructions.
+ // 3 Operands: in this form, we can have 'INST R1, R2, imm', which is used
+ // for instructions like the IMULrri instructions.
//
- // 2 Operands: this is for things like mov that do not read a second input
//
assert(MI->getOperand(0).isRegister() &&
MI->getOperand(1).isRegister() &&
- (MI->getNumOperands() == 2 ||
- (MI->getNumOperands() == 3 &&
- (MI->getOperand(2).isRegister() ||
- MI->getOperand(2).isImmediate())))
+ (MI->getNumOperands() == 2 ||
+ (MI->getNumOperands() == 3 &&
+ (MI->getOperand(2).isImmediate())))
&& "Bad format for MRMSrcReg!");
- if (MI->getNumOperands() == 3 &&
- MI->getOperand(0).getReg() != MI->getOperand(1).getReg())
- O << "**";
- O << TII.getName(MI->getOpCode()) << " ";
+ O << TII.getName(MI->getOpcode()) << " ";
printOp(MI->getOperand(0));
-
- // If this is IMULri* instructions, print the non-two-address operand.
- if (MI->getNumOperands() == 3 && MI->getOperand(2).isImmediate()) {
- O << ", ";
- printOp(MI->getOperand(1));
- }
-
O << ", ";
- printOp(MI->getOperand(MI->getNumOperands()-1));
+ printOp(MI->getOperand(1));
+ if (MI->getNumOperands() == 3) {
+ O << ", ";
+ printOp(MI->getOperand(2));
+ }
O << "\n";
return;
}
//
assert(MI->getOperand(0).isRegister() &&
(MI->getNumOperands() == 1+4 && isMem(MI, 1)) ||
- (MI->getNumOperands() == 2+4 && MI->getOperand(1).isRegister() &&
- isMem(MI, 2))
- && "Bad format for MRMDestReg!");
- if (MI->getNumOperands() == 2+4 &&
- MI->getOperand(0).getReg() != MI->getOperand(1).getReg())
- O << "**";
-
- O << TII.getName(MI->getOpCode()) << " ";
+(MI->getNumOperands() == 2+4 && MI->getOperand(5).isImmediate() && isMem(MI, 1))
+ && "Bad format for MRMSrcMem!");
+ O << TII.getName(MI->getOpcode()) << " ";
printOp(MI->getOperand(0));
O << ", " << sizePtr(Desc) << " ";
- printMemReference(MI, MI->getNumOperands()-4);
+ printMemReference(MI, 1);
+ if (MI->getNumOperands() == 2+4) {
+ O << ", ";
+ printOp(MI->getOperand(5));
+ }
O << "\n";
return;
}
- case X86II::MRMS0r: case X86II::MRMS1r:
- case X86II::MRMS2r: case X86II::MRMS3r:
- case X86II::MRMS4r: case X86II::MRMS5r:
- case X86II::MRMS6r: case X86II::MRMS7r: {
+ case X86II::MRM0r: case X86II::MRM1r:
+ case X86II::MRM2r: case X86II::MRM3r:
+ case X86II::MRM4r: case X86II::MRM5r:
+ case X86II::MRM6r: case X86II::MRM7r: {
// In this form, the following are valid formats:
// 1. sete r
// 2. cmp reg, immediate
MI->getOperand(0).getReg() != MI->getOperand(1).getReg())
O << "**";
- O << TII.getName(MI->getOpCode()) << " ";
+ O << TII.getName(MI->getOpcode()) << " ";
printOp(MI->getOperand(0));
if (MI->getOperand(MI->getNumOperands()-1).isImmediate()) {
O << ", ";
return;
}
- case X86II::MRMS0m: case X86II::MRMS1m:
- case X86II::MRMS2m: case X86II::MRMS3m:
- case X86II::MRMS4m: case X86II::MRMS5m:
- case X86II::MRMS6m: case X86II::MRMS7m: {
+ case X86II::MRM0m: case X86II::MRM1m:
+ case X86II::MRM2m: case X86II::MRM3m:
+ case X86II::MRM4m: case X86II::MRM5m:
+ case X86II::MRM6m: case X86II::MRM7m: {
// In this form, the following are valid formats:
// 1. sete [m]
// 2. cmp [m], immediate
//
assert(MI->getNumOperands() >= 4 && MI->getNumOperands() <= 5 &&
isMem(MI, 0) && "Bad MRMSxM format!");
- assert((MI->getNumOperands() != 5 || MI->getOperand(4).isImmediate()) &&
+ assert((MI->getNumOperands() != 5 ||
+ (MI->getOperand(4).isImmediate() ||
+ MI->getOperand(4).isGlobalAddress())) &&
"Bad MRMSxM format!");
+
+ const MachineOperand &Op3 = MI->getOperand(3);
+
// Bug: The 80-bit FP store-pop instruction "fstp XWORD PTR [...]"
// is misassembled by gas in intel_syntax mode as its 32-bit
// equivalent "fstp DWORD PTR [...]". Workaround: Output the raw
// opcode bytes instead of the instruction.
- if (MI->getOpCode() == X86::FSTPr80) {
+ if (MI->getOpcode() == X86::FSTP80m) {
if ((MI->getOperand(0).getReg() == X86::ESP)
&& (MI->getOperand(1).getImmedValue() == 1)) {
- int DispVal = MI->getOperand(3).getImmedValue();
- if ((DispVal < -128) || (DispVal > 127)) { // 4 byte disp.
- unsigned int val = (unsigned int) DispVal;
+ if (Op3.isImmediate() &&
+ Op3.getImmedValue() >= -128 && Op3.getImmedValue() <= 127) {
+ // 1 byte disp.
+ O << ".byte 0xdb, 0x7c, 0x24, 0x" << std::hex
+ << ((unsigned)Op3.getImmedValue() & 255) << std::dec << "\t# ";
+ } else {
O << ".byte 0xdb, 0xbc, 0x24\n\t";
- O << ".long 0x" << std::hex << (unsigned) val << std::dec << "\t# ";
- } else { // 1 byte disp.
- unsigned char val = (unsigned char) DispVal;
- O << ".byte 0xdb, 0x7c, 0x24, 0x" << std::hex << (unsigned) val
- << std::dec << "\t# ";
+ O << ".long ";
+ printOp(Op3);
+ O << "\t# ";
}
}
}
+
// Bug: The 80-bit FP load instruction "fld XWORD PTR [...]" is
// misassembled by gas in intel_syntax mode as its 32-bit
// equivalent "fld DWORD PTR [...]". Workaround: Output the raw
// opcode bytes instead of the instruction.
- if (MI->getOpCode() == X86::FLDr80) {
- if ((MI->getOperand(0).getReg() == X86::ESP)
- && (MI->getOperand(1).getImmedValue() == 1)) {
- int DispVal = MI->getOperand(3).getImmedValue();
- if ((DispVal < -128) || (DispVal > 127)) { // 4 byte disp.
- unsigned int val = (unsigned int) DispVal;
- O << ".byte 0xdb, 0xac, 0x24\n\t";
- O << ".long 0x" << std::hex << (unsigned) val << std::dec << "\t# ";
- } else { // 1 byte disp.
- unsigned char val = (unsigned char) DispVal;
- O << ".byte 0xdb, 0x6c, 0x24, 0x" << std::hex << (unsigned) val
- << std::dec << "\t# ";
- }
+ if (MI->getOpcode() == X86::FLD80m &&
+ MI->getOperand(0).getReg() == X86::ESP &&
+ MI->getOperand(1).getImmedValue() == 1) {
+ if (Op3.isImmediate() && Op3.getImmedValue() >= -128 &&
+ Op3.getImmedValue() <= 127) { // 1 byte displacement
+ O << ".byte 0xdb, 0x6c, 0x24, 0x" << std::hex
+ << ((unsigned)Op3.getImmedValue() & 255) << std::dec << "\t# ";
+ } else {
+ O << ".byte 0xdb, 0xac, 0x24\n\t";
+ O << ".long ";
+ printOp(Op3);
+ O << "\t# ";
}
}
+
// Bug: gas intel_syntax mode treats "fild QWORD PTR [...]" as an
// invalid opcode, saying "64 bit operations are only supported in
// 64 bit modes." libopcodes disassembles it as "fild DWORD PTR
// [...]", which is wrong. Workaround: Output the raw opcode bytes
// instead of the instruction.
- if (MI->getOpCode() == X86::FILDr64) {
- if ((MI->getOperand(0).getReg() == X86::ESP)
- && (MI->getOperand(1).getImmedValue() == 1)) {
- int DispVal = MI->getOperand(3).getImmedValue();
- if ((DispVal < -128) || (DispVal > 127)) { // 4 byte disp.
- unsigned int val = (unsigned int) DispVal;
- O << ".byte 0xdf, 0xac, 0x24\n\t";
- O << ".long 0x" << std::hex << (unsigned) val << std::dec << "\t# ";
- } else { // 1 byte disp.
- unsigned char val = (unsigned char) DispVal;
- O << ".byte 0xdf, 0x6c, 0x24, 0x" << std::hex << (unsigned) val
- << std::dec << "\t# ";
- }
+ if (MI->getOpcode() == X86::FILD64m &&
+ MI->getOperand(0).getReg() == X86::ESP &&
+ MI->getOperand(1).getImmedValue() == 1) {
+ if (Op3.isImmediate() && Op3.getImmedValue() >= -128 &&
+ Op3.getImmedValue() <= 127) { // 1 byte displacement
+ O << ".byte 0xdf, 0x6c, 0x24, 0x" << std::hex
+ << ((unsigned)Op3.getImmedValue() & 255) << std::dec << "\t# ";
+ } else {
+ O << ".byte 0xdf, 0xac, 0x24\n\t";
+ O << ".long ";
+ printOp(Op3);
+ O << std::dec << "\t# ";
}
}
+
// Bug: gas intel_syntax mode treats "fistp QWORD PTR [...]" as
// an invalid opcode, saying "64 bit operations are only
// supported in 64 bit modes." libopcodes disassembles it as
// "fistpll DWORD PTR [...]", which is wrong. Workaround: Output
// "fistpll DWORD PTR " instead, which is what libopcodes is
// expecting to see.
- if (MI->getOpCode() == X86::FISTPr64) {
+ if (MI->getOpcode() == X86::FISTP64m) {
O << "fistpll DWORD PTR ";
printMemReference(MI, 0);
if (MI->getNumOperands() == 5) {
O << "\t# ";
}
- O << TII.getName(MI->getOpCode()) << " ";
+ O << TII.getName(MI->getOpcode()) << " ";
O << sizePtr(Desc) << " ";
printMemReference(MI, 0);
if (MI->getNumOperands() == 5) {
delete Mang;
return false; // success
}
-
-} // End llvm namespace
projects / oota-llvm.git / blobdiff