Removed spurious EnablePPCRS check.

[oota-llvm.git] / lib / Target / X86 / README-X86-64.txt

diff --git a/lib/Target/X86/README-X86-64.txt b/lib/Target/X86/README-X86-64.txt
index 44c2e2894d9ffe2f0d3c49ccdf5bc5c851bceee0..359b83d01a6efd88b550e3f95864117b6c483690 100644 (file)
--- a/lib/Target/X86/README-X86-64.txt
+++ b/lib/Target/X86/README-X86-64.txt
@@ -28,27 +28,6 @@ _bar:
 
 We need to do the tailcall optimization as well.
 
-//===---------------------------------------------------------------------===//
-
-For this:
-
-int test(int a)
-{
-  return a * 3;
-}
-
-We generates
-       leal (%edi,%edi,2), %eax
-
-We should be generating 
-       leal (%rdi,%rdi,2), %eax
-
-instead. The later form does not require an address-size prefix 67H.
-
-It's probably ok to simply emit the corresponding 64-bit super class registers
-in this case?
-
-
 //===---------------------------------------------------------------------===//
 
 AMD64 Optimization Manual 8.2 has some nice information about optimizing integer
@@ -242,3 +221,18 @@ we were to support medium or larger code models, we need to use the movabs
 instruction. We should probably introduce something like AbsoluteAddress to
 distinguish it from GlobalAddress so the asm printer and JIT code emitter can
 do the right thing.
+
+//===---------------------------------------------------------------------===//
+
+It's not possible to reference AH, BH, CH, and DH registers in an instruction
+requiring REX prefix. However, divb and mulb both produce results in AH. If isel
+emits a CopyFromReg which gets turned into a movb and that can be allocated a
+r8b - r15b.
+
+To get around this, isel emits a CopyFromReg from AX and then right shift it
+down by 8 and truncate it. It's not pretty but it works. We need some register
+allocation magic to make the hack go away (e.g. putting additional constraints
+on the result of the movb).
+
+//===---------------------------------------------------------------------===//
+