Switch over to tablegen generated header files

[oota-llvm.git] / lib / Target / X86 / X86.h

diff --git a/lib/Target/X86/X86.h b/lib/Target/X86/X86.h
index 10bc017993ce1be4bf4a2e7990a447e6ec0edaf0..9cb15c383c6f48ce7afe5c29f74cde7985fbf1ab 100644 (file)
--- a/lib/Target/X86/X86.h
+++ b/lib/Target/X86/X86.h
@@ -3,8 +3,6 @@
 // This file contains the entry points for global functions defined in the x86
 // target library, as used by the LLVM JIT.
 //
-// FIXME: This file will be dramatically changed in the future
-//
 //===----------------------------------------------------------------------===//
 
 #ifndef TARGET_X86_H
@@ -14,45 +12,48 @@
 class TargetMachine;
 class Pass;
 
-/// createSimpleX86InstructionSelector - This pass converts an LLVM function
-/// into a machine code representation is a very simple peep-hole fashion.  The
+/// createX86SimpleInstructionSelector - This pass converts an LLVM function
+/// into a machine code representation in a very simple peep-hole fashion.  The
 /// generated code sucks but the implementation is nice and simple.
 ///
-Pass *createSimpleX86InstructionSelector(TargetMachine &TM);
+Pass *createX86SimpleInstructionSelector(TargetMachine &TM);
+
+/// createX86PeepholeOptimizer - Create a pass to perform X86 specific peephole
+/// optimizations.
+///
+Pass *createX86PeepholeOptimizerPass();
 
-/// X86SimpleRegisterAllocation - This function converts the specified machine
-/// code function from SSA form to use explicit registers by spilling every
-/// register.  Wow, great policy huh?
+/// createX86FloatingPointStackifierPass - This function returns a pass which
+/// converts floating point register references and pseudo instructions into
+/// floating point stack references and physical instructions.
 ///
-Pass *createSimpleX86RegisterAllocator(TargetMachine &TM);
+Pass *createX86FloatingPointStackifierPass();
 
-/// createX86CodePrinterPass - Print out the specified machine code function to
-/// the specified stream.  This function should work regardless of whether or
-/// not the function is in SSA form or not.
+/// createX86CodePrinterPass - Returns a pass that prints the X86
+/// assembly code for a MachineFunction to the given output stream,
+/// using the given target machine description.  This should work
+/// regardless of whether the function is in SSA form.
 ///
-Pass *createX86CodePrinterPass(TargetMachine &TM, std::ostream &O);
+Pass *createX86CodePrinterPass(std::ostream &o, TargetMachine &tm);
 
 /// X86EmitCodeToMemory - This function converts a register allocated function
 /// into raw machine code in a dynamically allocated chunk of memory.  A pointer
 /// to the start of the function is returned.
 ///
-Pass *createEmitX86CodeToMemory(TargetMachine &TM);
+Pass *createEmitX86CodeToMemory();
 
-// Put symbolic names in a namespace to avoid causing these to clash with all
-// kinds of other things...
+// Defines symbolic names for X86 registers.  This defines a mapping from
+// register name to register number.
 //
-namespace X86 {
-  // Defines a large number of symbolic names for X86 registers.  This defines a
-  // mapping from register name to register number.
-  //
-  enum Register {
-#define R(ENUM, NAME, FLAGS, TSFLAGS) ENUM,
-#include "X86RegisterInfo.def"
-  };
+#include "X86GenRegisterNames.inc"
 
+/// X86 namespace - This namespace contains all of the register and opcode enums
+/// used by the X86 backend.
+///
+namespace X86 {
   // This defines a large number of symbolic names for X86 instruction opcodes.
   enum Opcode {
-#define I(ENUM, NAME, BASEOPCODE, FLAGS, TSFLAGS) ENUM,
+#define I(ENUM, NAME, BASEOPCODE, FLAGS, TSFLAGS, IMPDEFS, IMPUSES) ENUM,
 #include "X86InstrInfo.def"
   };
 }