///
Pass *createSimpleX86InstructionSelector(TargetMachine &TM);
-/// X86SimpleRegisterAllocation - This function converts the specified machine
-/// code function from SSA form to use explicit registers by spilling every
-/// register. Wow, great policy huh?
+/// createSimpleRegisterAllocation - This function converts the specified
+/// machine code function from SSA form to use explicit registers by spilling
+/// every register. Wow, great policy huh?
///
-Pass *createSimpleX86RegisterAllocator(TargetMachine &TM);
+Pass *createSimpleRegisterAllocator(TargetMachine &TM);
+Pass *createLocalRegisterAllocator(TargetMachine &TM);
/// createX86CodePrinterPass - Print out the specified machine code function to
/// the specified stream. This function should work regardless of whether or
// mapping from register name to register number.
//
enum Register {
-#define R(ENUM, NAME, FLAGS, TSFLAGS) ENUM,
+#define R(ENUM, NAME, FLAGS, TSFLAGS, ALIAS_SET) ENUM,
#include "X86RegisterInfo.def"
};
// This defines a large number of symbolic names for X86 instruction opcodes.
enum Opcode {
-#define I(ENUM, NAME, FLAGS, TSFLAGS) ENUM,
+#define I(ENUM, NAME, BASEOPCODE, FLAGS, TSFLAGS, IMPDEFS, IMPUSES) ENUM,
#include "X86InstrInfo.def"
};
}