#include "X86.h"
#include "X86InstrInfo.h"
#include "llvm/Function.h"
+#include "llvm/Constant.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/MachineConstantPool.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "Support/Statistic.h"
namespace {
struct Printer : public MachineFunctionPass {
std::ostream &O;
-
- Printer(std::ostream &o) : O(o) {}
+ unsigned ConstIdx;
+ Printer(std::ostream &o) : O(o), ConstIdx(0) {}
virtual const char *getPassName() const {
return "X86 Assembly Printer";
}
+ void printConstantPool(MachineConstantPool *MCP, const TargetData &TD);
bool runOnMachineFunction(MachineFunction &F);
};
}
}
+// printConstantPool - Print out any constants which have been spilled to
+// memory...
+void Printer::printConstantPool(MachineConstantPool *MCP, const TargetData &TD){
+ const std::vector<Constant*> &CP = MCP->getConstants();
+ if (CP.empty()) return;
+
+ for (unsigned i = 0, e = CP.size(); i != e; ++i) {
+ O << "\t.section .rodata\n";
+ O << "\t.align " << (unsigned)TD.getTypeAlignment(CP[i]->getType()) << "\n";
+ O << ".CPI" << i+ConstIdx << ":\t\t\t\t\t;" << *CP[i] << "\n";
+ O << "\t*Constant output not implemented yet!*\n\n";
+ }
+ ConstIdx += CP.size(); // Don't recycle constant pool index numbers
+}
+
/// runOnFunction - This uses the X86InstructionInfo::print method
/// to print assembly for each instruction.
bool Printer::runOnMachineFunction(MachineFunction &MF) {
static unsigned BBNumber = 0;
const TargetMachine &TM = MF.getTarget();
- const MachineInstrInfo &MII = TM.getInstrInfo();
+ const TargetInstrInfo &TII = TM.getInstrInfo();
+
+ // Print out constants referenced by the function
+ printConstantPool(MF.getConstantPool(), TM.getTargetData());
// Print out labels for the function.
+ O << "\t.text\n";
+ O << "\t.align 16\n";
O << "\t.globl\t" << MF.getFunction()->getName() << "\n";
O << "\t.type\t" << MF.getFunction()->getName() << ", @function\n";
O << MF.getFunction()->getName() << ":\n";
II != E; ++II) {
// Print the assembly for the instruction.
O << "\t";
- MII.print(*II, O, TM);
+ TII.print(*II, O, TM);
}
}
}
static bool isMem(const MachineInstr *MI, unsigned Op) {
+ if (MI->getOperand(Op).isFrameIndex()) return true;
+ if (MI->getOperand(Op).isConstantPoolIndex()) return true;
return Op+4 <= MI->getNumOperands() &&
MI->getOperand(Op ).isRegister() &&isScale(MI->getOperand(Op+1)) &&
MI->getOperand(Op+2).isRegister() &&MI->getOperand(Op+3).isImmediate();
O << "<" << V->getName() << ">";
return;
}
+ // FALLTHROUGH
case MachineOperand::MO_MachineRegister:
if (MO.getReg() < MRegisterInfo::FirstVirtualRegister)
O << RI.get(MO.getReg()).Name;
case MachineOperand::MO_PCRelativeDisp:
O << "<" << MO.getVRegValue()->getName() << ">";
return;
+ case MachineOperand::MO_GlobalAddress:
+ O << "<" << MO.getGlobal()->getName() << ">";
+ return;
+ case MachineOperand::MO_ExternalSymbol:
+ O << "<" << MO.getSymbolName() << ">";
+ return;
default:
O << "<unknown op ty>"; return;
}
}
-static const std::string sizePtr(const MachineInstrDescriptor &Desc) {
+static const std::string sizePtr(const TargetInstrDescriptor &Desc) {
switch (Desc.TSFlags & X86II::ArgMask) {
default: assert(0 && "Unknown arg size!");
case X86II::Arg8: return "BYTE PTR";
case X86II::Arg16: return "WORD PTR";
case X86II::Arg32: return "DWORD PTR";
+ case X86II::Arg64: return "QWORD PTR";
case X86II::ArgF32: return "DWORD PTR";
case X86II::ArgF64: return "QWORD PTR";
case X86II::ArgF80: return "XWORD PTR";
static void printMemReference(std::ostream &O, const MachineInstr *MI,
unsigned Op, const MRegisterInfo &RI) {
assert(isMem(MI, Op) && "Invalid memory reference!");
+
+ if (MI->getOperand(Op).isFrameIndex()) {
+ O << "[frame slot #" << MI->getOperand(Op).getFrameIndex();
+ if (MI->getOperand(Op+3).getImmedValue())
+ O << " + " << MI->getOperand(Op+3).getImmedValue();
+ O << "]";
+ return;
+ } else if (MI->getOperand(Op).isConstantPoolIndex()) {
+ O << "[.CPI" << MI->getOperand(Op).getConstantPoolIndex();
+ if (MI->getOperand(Op+3).getImmedValue())
+ O << " + " << MI->getOperand(Op+3).getImmedValue();
+ O << "]";
+ return;
+ }
+
const MachineOperand &BaseReg = MI->getOperand(Op);
int ScaleVal = MI->getOperand(Op+1).getImmedValue();
const MachineOperand &IndexReg = MI->getOperand(Op+2);
void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O,
const TargetMachine &TM) const {
unsigned Opcode = MI->getOpcode();
- const MachineInstrDescriptor &Desc = get(Opcode);
+ const TargetInstrDescriptor &Desc = get(Opcode);
switch (Desc.TSFlags & X86II::FormMask) {
case X86II::Pseudo:
}
} else {
unsigned i = 0;
- if (MI->getNumOperands() && MI->getOperand(0).opIsDef()) {
+ if (MI->getNumOperands() && (MI->getOperand(0).opIsDefOnly() ||
+ MI->getOperand(0).opIsDefAndUse())) {
printOp(O, MI->getOperand(0), RI);
O << " = ";
++i;
for (unsigned e = MI->getNumOperands(); i != e; ++i) {
O << " ";
- if (MI->getOperand(i).opIsDef()) O << "*";
+ if (MI->getOperand(i).opIsDefOnly() ||
+ MI->getOperand(i).opIsDefAndUse()) O << "*";
printOp(O, MI->getOperand(i), RI);
- if (MI->getOperand(i).opIsDef()) O << "*";
+ if (MI->getOperand(i).opIsDefOnly() ||
+ MI->getOperand(i).opIsDefAndUse()) O << "*";
}
}
O << "\n";
// The accepted forms of Raw instructions are:
// 1. nop - No operand required
// 2. jmp foo - PC relative displacement operand
+ // 3. call bar - GlobalAddress Operand or External Symbol Operand
//
assert(MI->getNumOperands() == 0 ||
- (MI->getNumOperands() == 1 && MI->getOperand(0).isPCRelativeDisp())&&
+ (MI->getNumOperands() == 1 &&
+ (MI->getOperand(0).isPCRelativeDisp() ||
+ MI->getOperand(0).isGlobalAddress() ||
+ MI->getOperand(0).isExternalSymbol())) &&
"Illegal raw instruction!");
O << getName(MI->getOpcode()) << " ";
(MI->getNumOperands() == 2 &&
(MI->getOperand(1).getVRegValueOrNull() ||
MI->getOperand(1).isImmediate() ||
- MI->getOperand(1).isRegister()))) &&
+ MI->getOperand(1).isRegister() ||
+ MI->getOperand(1).isGlobalAddress() ||
+ MI->getOperand(1).isExternalSymbol()))) &&
"Illegal form for AddRegFrm instruction!");
unsigned Reg = MI->getOperand(0).getReg();
O << getName(MI->getOpCode()) << " ";
printOp(O, MI->getOperand(0), RI);
- if (MI->getNumOperands() == 2 && !MI->getOperand(1).isRegister()) {
+ if (MI->getNumOperands() == 2 &&
+ (!MI->getOperand(1).isRegister() ||
+ MI->getOperand(1).getVRegValueOrNull() ||
+ MI->getOperand(1).isGlobalAddress() ||
+ MI->getOperand(1).isExternalSymbol())) {
O << ", ";
printOp(O, MI->getOperand(1), RI);
}
return;
}
case X86II::MRMDestReg: {
- // There are two acceptable forms of MRMDestReg instructions, those with 3
- // and 2 operands:
+ // There are two acceptable forms of MRMDestReg instructions, those with 2,
+ // 3 and 4 operands:
+ //
+ // 2 Operands: this is for things like mov that do not read a second input
//
// 3 Operands: in this form, the first two registers (the destination, and
// the first operand) should be the same, post register allocation. The 3rd
// operand is an additional input. This should be for things like add
// instructions.
//
- // 2 Operands: this is for things like mov that do not read a second input
+ // 4 Operands: This form is for instructions which are 3 operands forms, but
+ // have a constant argument as well.
//
+ bool isTwoAddr = isTwoAddrInstr(Opcode);
assert(MI->getOperand(0).isRegister() &&
- (MI->getNumOperands() == 2 ||
- (MI->getNumOperands() == 3 && MI->getOperand(1).isRegister())) &&
- MI->getOperand(MI->getNumOperands()-1).isRegister()
+ (MI->getNumOperands() == 2 ||
+ (isTwoAddr && MI->getOperand(1).isRegister() &&
+ MI->getOperand(0).getReg() == MI->getOperand(1).getReg() &&
+ (MI->getNumOperands() == 3 ||
+ (MI->getNumOperands() == 4 && MI->getOperand(3).isImmediate()))))
&& "Bad format for MRMDestReg!");
- if (MI->getNumOperands() == 3 &&
- MI->getOperand(0).getReg() != MI->getOperand(1).getReg())
- O << "**";
O << getName(MI->getOpCode()) << " ";
printOp(O, MI->getOperand(0), RI);
O << ", ";
- printOp(O, MI->getOperand(MI->getNumOperands()-1), RI);
+ printOp(O, MI->getOperand(1+isTwoAddr), RI);
+ if (MI->getNumOperands() == 4) {
+ O << ", ";
+ printOp(O, MI->getOperand(3), RI);
+ }
O << "\n";
return;
}
assert(isMem(MI, 0) && MI->getNumOperands() == 4+1 &&
MI->getOperand(4).isRegister() && "Bad format for MRMDestMem!");
- O << getName(MI->getOpCode()) << " " << sizePtr (Desc) << " ";
+ O << getName(MI->getOpCode()) << " " << sizePtr(Desc) << " ";
printMemReference(O, MI, 0, RI);
O << ", ";
printOp(O, MI->getOperand(4), RI);
MI->getOperand(1).isRegister() &&
(MI->getNumOperands() == 2 ||
(MI->getNumOperands() == 3 && MI->getOperand(2).isRegister()))
- && "Bad format for MRMDestReg!");
+ && "Bad format for MRMSrcReg!");
if (MI->getNumOperands() == 3 &&
MI->getOperand(0).getReg() != MI->getOperand(1).getReg())
O << "**";
O << getName(MI->getOpCode()) << " ";
printOp(O, MI->getOperand(0), RI);
- O << ", " << sizePtr (Desc) << " ";
+ O << ", " << sizePtr(Desc) << " ";
printMemReference(O, MI, MI->getNumOperands()-4, RI);
O << "\n";
return;
return;
}
+ case X86II::MRMS0m: case X86II::MRMS1m:
+ case X86II::MRMS2m: case X86II::MRMS3m:
+ case X86II::MRMS4m: case X86II::MRMS5m:
+ case X86II::MRMS6m: case X86II::MRMS7m: {
+ // In this form, the following are valid formats:
+ // 1. sete [m]
+ // 2. cmp [m], immediate
+ // 2. shl [m], rinput <implicit CL or 1>
+ // 3. sbb [m], immediate
+ //
+ assert(MI->getNumOperands() >= 4 && MI->getNumOperands() <= 5 &&
+ isMem(MI, 0) && "Bad MRMSxM format!");
+ assert((MI->getNumOperands() != 5 || MI->getOperand(4).isImmediate()) &&
+ "Bad MRMSxM format!");
+
+ O << getName(MI->getOpCode()) << " ";
+ O << sizePtr(Desc) << " ";
+ printMemReference(O, MI, 0, RI);
+ if (MI->getNumOperands() == 5) {
+ O << ", ";
+ printOp(O, MI->getOperand(4), RI);
+ }
+ O << "\n";
+ return;
+ }
+
default:
- O << "\t\t\t-"; MI->print(O, TM); break;
+ O << "\tUNKNOWN FORM:\t\t-"; MI->print(O, TM); break;
}
}
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