MachineFunction & MF = MachineFunction::get (&F);
const MachineInstrInfo & MII = TM.getInstrInfo ();
- O << "; x86 printing only sorta implemented so far!\n";
-
// Print out labels for the function.
O << "\t.globl\t" << F.getName () << "\n";
O << "\t.type\t" << F.getName () << ", @function\n";
return false;
}
+static bool isScale(const MachineOperand &MO) {
+ return MO.isImmediate() &&
+ (MO.getImmedValue() == 1 || MO.getImmedValue() == 2 ||
+ MO.getImmedValue() == 4 || MO.getImmedValue() == 8);
+}
+
+static bool isMem(const MachineInstr *MI, unsigned Op) {
+ return Op+4 <= MI->getNumOperands() &&
+ MI->getOperand(Op ).isRegister() &&isScale(MI->getOperand(Op+1)) &&
+ MI->getOperand(Op+2).isRegister() &&MI->getOperand(Op+3).isImmediate();
+}
+
static void printOp(std::ostream &O, const MachineOperand &MO,
const MRegisterInfo &RI) {
switch (MO.getType()) {
case MachineOperand::MO_VirtualRegister:
+ if (Value *V = MO.getVRegValueOrNull()) {
+ O << "<" << V->getName() << ">";
+ return;
+ }
case MachineOperand::MO_MachineRegister:
if (MO.getReg() < MRegisterInfo::FirstVirtualRegister)
O << RI.get(MO.getReg()).Name;
case MachineOperand::MO_UnextendedImmed:
O << (int)MO.getImmedValue();
return;
+ case MachineOperand::MO_PCRelativeDisp:
+ O << "<" << MO.getVRegValue()->getName() << ">";
+ return;
default:
O << "<unknown op ty>"; return;
}
}
-static inline void toHexDigit(std::ostream &O, unsigned char V) {
- if (V >= 10)
- O << (char)('A'+V-10);
- else
- O << (char)('0'+V);
-}
-
-static std::ostream &toHex(std::ostream &O, unsigned char V) {
- toHexDigit(O, V >> 4);
- toHexDigit(O, V & 0xF);
- return O;
-}
-
-static std::ostream &emitConstant(std::ostream &O, unsigned Val, unsigned Size){
- // Output the constant in little endian byte order...
- for (unsigned i = 0; i != Size; ++i) {
- toHex(O, Val) << " ";
- Val >>= 8;
+static const std::string sizePtr (const MachineInstrDescriptor &Desc) {
+ switch (Desc.TSFlags & X86II::ArgMask) {
+ case X86II::Arg8: return "BYTE PTR";
+ case X86II::Arg16: return "WORD PTR";
+ case X86II::Arg32: return "DWORD PTR";
+ case X86II::Arg64: return "QWORD PTR";
+ case X86II::Arg80: return "XWORD PTR";
+ case X86II::Arg128: return "128BIT PTR"; // dunno what the real one is
+ default: return "<SIZE?> PTR"; // crack being smoked
}
- return O;
-}
-
-
-static bool isReg(const MachineOperand &MO) {
- return MO.getType() == MachineOperand::MO_VirtualRegister ||
- MO.getType() == MachineOperand::MO_MachineRegister;
-}
-
-static bool isImmediate(const MachineOperand &MO) {
- return MO.getType() == MachineOperand::MO_SignExtendedImmed ||
- MO.getType() == MachineOperand::MO_UnextendedImmed;
}
-
-// getX86RegNum - This function maps LLVM register identifiers to their X86
-// specific numbering, which is used in various places encoding instructions.
-//
-static unsigned getX86RegNum(unsigned RegNo) {
- switch(RegNo) {
- case X86::EAX: case X86::AX: case X86::AL: return 0;
- case X86::ECX: case X86::CX: case X86::CL: return 1;
- case X86::EDX: case X86::DX: case X86::DL: return 2;
- case X86::EBX: case X86::BX: case X86::BL: return 3;
- case X86::ESP: case X86::SP: case X86::AH: return 4;
- case X86::EBP: case X86::BP: case X86::CH: return 5;
- case X86::ESI: case X86::SI: case X86::DH: return 6;
- case X86::EDI: case X86::DI: case X86::BH: return 7;
- default:
- assert(RegNo >= MRegisterInfo::FirstVirtualRegister &&
- "Unknown physical register!");
- DEBUG(std::cerr << "Register allocator hasn't allocated " << RegNo
- << " correctly yet!\n");
- return 0;
+static void printMemReference(std::ostream &O, const MachineInstr *MI,
+ unsigned Op, const MRegisterInfo &RI) {
+ assert(isMem(MI, Op) && "Invalid memory reference!");
+ const MachineOperand &BaseReg = MI->getOperand(Op);
+ const MachineOperand &Scale = MI->getOperand(Op+1);
+ const MachineOperand &IndexReg = MI->getOperand(Op+2);
+ const MachineOperand &Disp = MI->getOperand(Op+3);
+
+ O << "[";
+ bool NeedPlus = false;
+ if (BaseReg.getReg()) {
+ printOp(O, BaseReg, RI);
+ NeedPlus = true;
}
-}
-inline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode,
- unsigned RM) {
- assert(Mod < 4 && RegOpcode < 8 && RM < 8 && "ModRM Fields out of range!");
- return RM | (RegOpcode << 3) | (Mod << 6);
-}
+ if (IndexReg.getReg()) {
+ if (NeedPlus) O << " + ";
+ if (Scale.getImmedValue() != 1)
+ O << Scale.getImmedValue() << "*";
+ printOp(O, IndexReg, RI);
+ NeedPlus = true;
+ }
-static unsigned char regModRMByte(unsigned ModRMReg, unsigned RegOpcodeField) {
- return ModRMByte(3, RegOpcodeField, getX86RegNum(ModRMReg));
+ if (Disp.getImmedValue()) {
+ if (NeedPlus) O << " + ";
+ printOp(O, Disp, RI);
+ }
+ O << "]";
}
-
// print - Print out an x86 instruction in intel syntax
void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O,
const TargetMachine &TM) const {
unsigned Opcode = MI->getOpcode();
const MachineInstrDescriptor &Desc = get(Opcode);
- // Print instruction prefixes if neccesary
-
- if (Desc.TSFlags & X86II::OpSize) O << "66 "; // Operand size...
- if (Desc.TSFlags & X86II::TB) O << "0F "; // Two-byte opcode prefix
+ if (Opcode == X86::PHI) {
+ printOp(O, MI->getOperand(0), RI);
+ O << " = phi ";
+ for (unsigned i = 1, e = MI->getNumOperands(); i != e; i+=2) {
+ if (i != 1) O << ", ";
+ O << "[";
+ printOp(O, MI->getOperand(i), RI);
+ O << ", ";
+ printOp(O, MI->getOperand(i+1), RI);
+ O << "]";
+ }
+ O << "\n";
+ return;
+ }
+
switch (Desc.TSFlags & X86II::FormMask) {
- case X86II::OtherFrm:
- O << "\t\t\t";
- O << "-"; MI->print(O, TM);
- break;
case X86II::RawFrm:
- toHex(O, getBaseOpcodeFor(Opcode));
- O << "\n\t\t\t\t";
+ // The accepted forms of Raw instructions are:
+ // 1. nop - No operand required
+ // 2. jmp foo - PC relative displacement operand
+ //
+ assert(MI->getNumOperands() == 0 ||
+ (MI->getNumOperands() == 1 && MI->getOperand(0).isPCRelativeDisp())&&
+ "Illegal raw instruction!");
O << getName(MI->getOpCode()) << " ";
- for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
- if (i) O << ", ";
- printOp(O, MI->getOperand(i), RI);
+ if (MI->getNumOperands() == 1) {
+ printOp(O, MI->getOperand(0), RI);
}
O << "\n";
return;
-
case X86II::AddRegFrm: {
// There are currently two forms of acceptable AddRegFrm instructions.
// Either the instruction JUST takes a single register (like inc, dec, etc),
// or it takes a register and an immediate of the same size as the register
- // (move immediate f.e.).
+ // (move immediate f.e.). Note that this immediate value might be stored as
+ // an LLVM value, to represent, for example, loading the address of a global
+ // into a register.
//
- assert(isReg(MI->getOperand(0)) &&
+ assert(MI->getOperand(0).isRegister() &&
(MI->getNumOperands() == 1 ||
- (MI->getNumOperands() == 2 && isImmediate(MI->getOperand(1)))) &&
+ (MI->getNumOperands() == 2 &&
+ (MI->getOperand(1).getVRegValueOrNull() ||
+ MI->getOperand(1).isImmediate()))) &&
"Illegal form for AddRegFrm instruction!");
unsigned Reg = MI->getOperand(0).getReg();
- toHex(O, getBaseOpcodeFor(Opcode) + getX86RegNum(Reg)) << " ";
-
- if (MI->getNumOperands() == 2) {
- unsigned Size = 4;
- emitConstant(O, MI->getOperand(1).getImmedValue(), Size);
- }
- O << "\n\t\t\t\t";
O << getName(MI->getOpCode()) << " ";
printOp(O, MI->getOperand(0), RI);
if (MI->getNumOperands() == 2) {
//
// 2 Operands: this is for things like mov that do not read a second input
//
- assert(isReg(MI->getOperand(0)) &&
+ assert(MI->getOperand(0).isRegister() &&
(MI->getNumOperands() == 2 ||
- (MI->getNumOperands() == 3 && isReg(MI->getOperand(1)))) &&
- isReg(MI->getOperand(MI->getNumOperands()-1))
+ (MI->getNumOperands() == 3 && MI->getOperand(1).isRegister())) &&
+ MI->getOperand(MI->getNumOperands()-1).isRegister()
&& "Bad format for MRMDestReg!");
if (MI->getNumOperands() == 3 &&
MI->getOperand(0).getReg() != MI->getOperand(1).getReg())
O << "**";
- toHex(O, getBaseOpcodeFor(Opcode)) << " ";
- unsigned ModRMReg = MI->getOperand(0).getReg();
- unsigned ExtraReg = MI->getOperand(MI->getNumOperands()-1).getReg();
- toHex(O, regModRMByte(ModRMReg, getX86RegNum(ExtraReg)));
-
- O << "\n\t\t\t\t";
O << getName(MI->getOpCode()) << " ";
printOp(O, MI->getOperand(0), RI);
O << ", ";
O << "\n";
return;
}
+
+ case X86II::MRMDestMem: {
+ // These instructions are the same as MRMDestReg, but instead of having a
+ // register reference for the mod/rm field, it's a memory reference.
+ //
+ assert(isMem(MI, 0) && MI->getNumOperands() == 4+1 &&
+ MI->getOperand(4).isRegister() && "Bad format for MRMDestMem!");
+
+ O << getName(MI->getOpCode()) << " " << sizePtr (Desc) << " ";
+ printMemReference(O, MI, 0, RI);
+ O << ", ";
+ printOp(O, MI->getOperand(4), RI);
+ O << "\n";
+ return;
+ }
+
case X86II::MRMSrcReg: {
// There is a two forms that are acceptable for MRMSrcReg instructions,
// those with 3 and 2 operands:
//
// 2 Operands: this is for things like mov that do not read a second input
//
- assert(isReg(MI->getOperand(0)) &&
- isReg(MI->getOperand(1)) &&
+ assert(MI->getOperand(0).isRegister() &&
+ MI->getOperand(1).isRegister() &&
(MI->getNumOperands() == 2 ||
- (MI->getNumOperands() == 3 && isReg(MI->getOperand(2))))
+ (MI->getNumOperands() == 3 && MI->getOperand(2).isRegister()))
&& "Bad format for MRMDestReg!");
if (MI->getNumOperands() == 3 &&
MI->getOperand(0).getReg() != MI->getOperand(1).getReg())
O << "**";
- toHex(O, getBaseOpcodeFor(Opcode)) << " ";
- unsigned ModRMReg = MI->getOperand(MI->getNumOperands()-1).getReg();
- unsigned ExtraReg = MI->getOperand(0).getReg();
- toHex(O, regModRMByte(ModRMReg, getX86RegNum(ExtraReg)));
-
- O << "\n\t\t\t\t";
O << getName(MI->getOpCode()) << " ";
printOp(O, MI->getOperand(0), RI);
O << ", ";
return;
}
+ case X86II::MRMSrcMem: {
+ // These instructions are the same as MRMSrcReg, but instead of having a
+ // register reference for the mod/rm field, it's a memory reference.
+ //
+ assert(MI->getOperand(0).isRegister() &&
+ (MI->getNumOperands() == 1+4 && isMem(MI, 1)) ||
+ (MI->getNumOperands() == 2+4 && MI->getOperand(1).isRegister() &&
+ isMem(MI, 2))
+ && "Bad format for MRMDestReg!");
+ if (MI->getNumOperands() == 2+4 &&
+ MI->getOperand(0).getReg() != MI->getOperand(1).getReg())
+ O << "**";
+
+ O << getName(MI->getOpCode()) << " ";
+ printOp(O, MI->getOperand(0), RI);
+ O << ", " << sizePtr (Desc) << " ";
+ printMemReference(O, MI, MI->getNumOperands()-4, RI);
+ O << "\n";
+ return;
+ }
+
case X86II::MRMS0r: case X86II::MRMS1r:
case X86II::MRMS2r: case X86II::MRMS3r:
case X86II::MRMS4r: case X86II::MRMS5r:
case X86II::MRMS6r: case X86II::MRMS7r: {
- unsigned ExtraField = (Desc.TSFlags & X86II::FormMask)-X86II::MRMS0r;
-
// In this form, the following are valid formats:
// 1. sete r
+ // 2. cmp reg, immediate
// 2. shl rdest, rinput <implicit CL or 1>
// 3. sbb rdest, rinput, immediate [rdest = rinput]
//
assert(MI->getNumOperands() > 0 && MI->getNumOperands() < 4 &&
- isReg(MI->getOperand(0)) && "Bad MRMSxR format!");
- assert((MI->getNumOperands() < 2 || isReg(MI->getOperand(1))) &&
+ MI->getOperand(0).isRegister() && "Bad MRMSxR format!");
+ assert((MI->getNumOperands() != 2 ||
+ MI->getOperand(1).isRegister() || MI->getOperand(1).isImmediate())&&
"Bad MRMSxR format!");
- assert((MI->getNumOperands() < 3 || isImmediate(MI->getOperand(2))) &&
+ assert((MI->getNumOperands() < 3 ||
+ (MI->getOperand(1).isRegister() && MI->getOperand(2).isImmediate())) &&
"Bad MRMSxR format!");
- if (MI->getNumOperands() > 1 &&
+ if (MI->getNumOperands() > 1 && MI->getOperand(1).isRegister() &&
MI->getOperand(0).getReg() != MI->getOperand(1).getReg())
O << "**";
- toHex(O, getBaseOpcodeFor(Opcode)) << " ";
- toHex(O, regModRMByte(MI->getOperand(0).getReg(), ExtraField));
-
- if (MI->getNumOperands() == 3) {
- unsigned Size = 4;
- emitConstant(O, MI->getOperand(1).getImmedValue(), Size);
- }
-
- O << "\n\t\t\t\t";
O << getName(MI->getOpCode()) << " ";
printOp(O, MI->getOperand(0), RI);
- if (MI->getNumOperands() == 3) {
+ if (MI->getOperand(MI->getNumOperands()-1).isImmediate()) {
O << ", ";
- printOp(O, MI->getOperand(2), RI);
+ printOp(O, MI->getOperand(MI->getNumOperands()-1), RI);
}
O << "\n";
return;
}
- case X86II::MRMDestMem:
- case X86II::MRMSrcMem:
default:
O << "\t\t\t-"; MI->print(O, TM); break;
}
projects / oota-llvm.git / blobdiff