Reapplying [FastISel][AArch64] Cleanup constant materialization code. NFCI.

[oota-llvm.git] / lib / Target / X86 / X86AtomicExpandPass.cpp

diff --git a/lib/Target/X86/X86AtomicExpandPass.cpp b/lib/Target/X86/X86AtomicExpandPass.cpp
index 2ba76091f28c23b6c8d405653a936785746ca3eb..3dcadb16760b741f345298ddce5428a258226fd4 100644 (file)
--- a/lib/Target/X86/X86AtomicExpandPass.cpp
+++ b/lib/Target/X86/X86AtomicExpandPass.cpp
@@ -90,30 +90,29 @@ bool X86AtomicExpandPass::runOnFunction(Function &F) {
       MadeChange |= expandAtomicRMW(AI);
     if (StoreInst *SI = dyn_cast<StoreInst>(Inst))
       MadeChange |= expandAtomicStore(SI);
+
+    assert(MadeChange && "Atomic inst not expanded when it should be?");
+    Inst->eraseFromParent();
   }
 
   return MadeChange;
 }
 
-/// Returns true if operations on the given type will need to use either
-/// cmpxchg8b or cmpxchg16b. This occurs if the type is 1 step up from the
-/// native width, and the instructions are available (otherwise we leave them
-/// alone to become __sync_fetch_and_... calls).
+/// Returns true if the operand type is 1 step up from the native width, and
+/// the corresponding cmpxchg8b or cmpxchg16b instruction is available
+/// (otherwise we leave them alone to become __sync_fetch_and_... calls).
 bool X86AtomicExpandPass::needsCmpXchgNb(llvm::Type *MemType) {
   const X86Subtarget &Subtarget = TM->getSubtarget<X86Subtarget>();
-  if (!Subtarget.hasCmpxchg16b())
-    return false;
-
-  unsigned CmpXchgNbWidth = Subtarget.is64Bit() ? 128 : 64;
-
   unsigned OpWidth = MemType->getPrimitiveSizeInBits();
-  if (OpWidth == CmpXchgNbWidth)
-    return true;
+
+  if (OpWidth == 64)
+    return !Subtarget.is64Bit();  // FIXME this should be Subtarget.hasCmpxchg8b
+  if (OpWidth == 128)
+    return Subtarget.hasCmpxchg16b();
 
   return false;
 }
 
-
 bool X86AtomicExpandPass::shouldExpandAtomicRMW(AtomicRMWInst *AI) {
   const X86Subtarget &Subtarget = TM->getSubtarget<X86Subtarget>();
   unsigned NativeWidth = Subtarget.is64Bit() ? 64 : 32;
@@ -259,7 +258,6 @@ bool X86AtomicExpandPass::expandAtomicRMW(AtomicRMWInst *AI) {
   Builder.CreateCondBr(Success, ExitBB, LoopBB);
 
   AI->replaceAllUsesWith(NewLoaded);
-  AI->eraseFromParent();
 
   return true;
 }
@@ -268,14 +266,18 @@ bool X86AtomicExpandPass::expandAtomicStore(StoreInst *SI) {
   // An atomic store might need cmpxchg16b (or 8b on x86) to execute. Express
   // this in terms of the usual expansion to "atomicrmw xchg".
   IRBuilder<> Builder(SI);
+  AtomicOrdering Order =
+      SI->getOrdering() == Unordered ? Monotonic : SI->getOrdering();
   AtomicRMWInst *AI =
       Builder.CreateAtomicRMW(AtomicRMWInst::Xchg, SI->getPointerOperand(),
-                              SI->getValueOperand(), SI->getOrdering());
-  SI->eraseFromParent();
+                              SI->getValueOperand(), Order);
 
   // Now we have an appropriate swap instruction, lower it as usual.
-  if (shouldExpandAtomicRMW(AI))
-    return expandAtomicRMW(AI);
+  if (shouldExpandAtomicRMW(AI)) {
+    expandAtomicRMW(AI);
+    AI->eraseFromParent();
+    return true;
+  }
 
   return AI;
 }