#include "llvm/CodeGen/MachineCodeEmitter.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstr.h"
+#include "llvm/Value.h"
namespace {
class Emitter : public FunctionPass {
bool runOnFunction(Function &F);
+ virtual const char *getPassName() const {
+ return "X86 Machine Code Emitter";
+ }
+
private:
void emitBasicBlock(MachineBasicBlock &MBB);
void emitInstruction(MachineInstr &MI);
emitConstant(Disp.getImmedValue(), 1);
} else {
// Emit the most general non-SIB encoding: [REG+disp32]
- MCE.emitByte(ModRMByte(1, RegOpcodeField, BaseRegNo));
+ MCE.emitByte(ModRMByte(2, RegOpcodeField, BaseRegNo));
emitConstant(Disp.getImmedValue(), 4);
}
}
assert(IndexReg.getReg() != X86::ESP && "Cannot use ESP as index reg!");
bool ForceDisp32 = false;
+ bool ForceDisp8 = false;
if (BaseReg.getReg() == 0) {
// If there is no base register, we emit the special case SIB byte with
// MOD=0, BASE=5, to JUST get the index, scale, and displacement.
MCE.emitByte(ModRMByte(0, RegOpcodeField, 4));
ForceDisp32 = true;
- } else if (Disp.getImmedValue() == 0) {
+ } else if (Disp.getImmedValue() == 0 && BaseReg.getReg() != X86::EBP) {
// Emit no displacement ModR/M byte
MCE.emitByte(ModRMByte(0, RegOpcodeField, 4));
} else if (isDisp8(Disp.getImmedValue())) {
// Emit the disp8 encoding...
MCE.emitByte(ModRMByte(1, RegOpcodeField, 4));
+ ForceDisp8 = true; // Make sure to force 8 bit disp if Base=EBP
} else {
// Emit the normal disp32 encoding...
MCE.emitByte(ModRMByte(2, RegOpcodeField, 4));
}
// Do we need to output a displacement?
- if (Disp.getImmedValue() != 0 || ForceDisp32) {
+ if (Disp.getImmedValue() != 0 || ForceDisp32 || ForceDisp8) {
if (!ForceDisp32 && isDisp8(Disp.getImmedValue()))
emitConstant(Disp.getImmedValue(), 1);
else
}
}
-static bool isImmediate(const MachineOperand &MO) {
- return MO.getType() == MachineOperand::MO_SignExtendedImmed ||
- MO.getType() == MachineOperand::MO_UnextendedImmed;
+unsigned sizeOfPtr (const MachineInstrDescriptor &Desc) {
+ switch (Desc.TSFlags & X86II::ArgMask) {
+ case X86II::Arg8: return 1;
+ case X86II::Arg16: return 2;
+ case X86II::Arg32: return 4;
+ case X86II::Arg64: return 8;
+ case X86II::Arg80: return 10;
+ case X86II::Arg128: return 16;
+ default: assert(0 && "Memory size not set!");
+ }
}
+
void Emitter::emitInstruction(MachineInstr &MI) {
unsigned Opcode = MI.getOpcode();
const MachineInstrDescriptor &Desc = II.get(Opcode);
case X86II::AddRegFrm:
MCE.emitByte(BaseOpcode + getX86RegNum(MI.getOperand(0).getReg()));
if (MI.getNumOperands() == 2) {
- unsigned Size = 4;
- emitConstant(MI.getOperand(1).getImmedValue(), Size);
+ unsigned Size = sizeOfPtr(Desc);
+ if (Value *V = MI.getOperand(1).getVRegValueOrNull()) {
+ assert(Size == 4 && "Don't know how to emit non-pointer values!");
+ MCE.emitGlobalAddress(cast<GlobalValue>(V));
+ } else {
+ emitConstant(MI.getOperand(1).getImmedValue(), Size);
+ }
}
break;
case X86II::MRMDestReg:
emitRegModRMByte(MI.getOperand(0).getReg(),
(Desc.TSFlags & X86II::FormMask)-X86II::MRMS0r);
- if (isImmediate(MI.getOperand(MI.getNumOperands()-1))) {
- unsigned Size = 4;
+ if (MI.getOperand(MI.getNumOperands()-1).isImmediate()) {
+ unsigned Size = sizeOfPtr(Desc);
emitConstant(MI.getOperand(MI.getNumOperands()-1).getImmedValue(), Size);
}
break;
-
-
}
}