Add some ADD instructions that take memory operands for Alkis

[oota-llvm.git] / lib / Target / X86 / X86CodeEmitter.cpp

diff --git a/lib/Target/X86/X86CodeEmitter.cpp b/lib/Target/X86/X86CodeEmitter.cpp
index 13e9d762f5d59c76143f744a35e15baa115cd82f..a28d0ee86db8ca2a21f85a13c3b8f68fa325a1b9 100644 (file)
--- a/lib/Target/X86/X86CodeEmitter.cpp
+++ b/lib/Target/X86/X86CodeEmitter.cpp
@@ -242,7 +242,7 @@ void Emitter::emitBasicBlock(MachineBasicBlock &MBB) {
     BasicBlockAddrs[MBB.getBasicBlock()] = Addr;
 
   for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E; ++I)
-    emitInstruction(**I);
+    emitInstruction(*I);
 }
 
 
@@ -329,7 +329,7 @@ static unsigned getX86RegNum(unsigned RegNo) {
   case X86::ST4: case X86::ST5: case X86::ST6: case X86::ST7:
     return RegNo-X86::ST0;
   default:
-    assert(RegNo >= MRegisterInfo::FirstVirtualRegister &&
+    assert(MRegisterInfo::isVirtualRegister(RegNo) &&
            "Unknown physical register!");
     assert(0 && "Register allocator hasn't allocated reg correctly yet!");
     return 0;
@@ -472,6 +472,9 @@ void Emitter::emitInstruction(MachineInstr &MI) {
   unsigned Opcode = MI.getOpcode();
   const TargetInstrDescriptor &Desc = II->get(Opcode);
 
+  // Emit the repeat opcode prefix as needed.
+  if ((Desc.TSFlags & X86II::Op0Mask) == X86II::REP) MCE.emitByte(0xF3);
+
   // Emit instruction prefixes if necessary
   if (Desc.TSFlags & X86II::OpSize) MCE.emitByte(0x66);// Operand size...
 
@@ -479,6 +482,7 @@ void Emitter::emitInstruction(MachineInstr &MI) {
   case X86II::TB:
     MCE.emitByte(0x0F);   // Two-byte opcode prefix
     break;
+  case X86II::REP: break; // already handled.
   case X86II::D8: case X86II::D9: case X86II::DA: case X86II::DB:
   case X86II::DC: case X86II::DD: case X86II::DE: case X86II::DF:
     MCE.emitByte(0xD8+
@@ -548,10 +552,10 @@ void Emitter::emitInstruction(MachineInstr &MI) {
 
   case X86II::MRMDestReg: {
     MCE.emitByte(BaseOpcode);
-    MachineOperand &SrcOp = MI.getOperand(1+II->isTwoAddrInstr(Opcode));
-    emitRegModRMByte(MI.getOperand(0).getReg(), getX86RegNum(SrcOp.getReg()));
-    if (MI.getNumOperands() == 4)
-      emitConstant(MI.getOperand(3).getImmedValue(), sizeOfPtr(Desc));
+    emitRegModRMByte(MI.getOperand(0).getReg(),
+                     getX86RegNum(MI.getOperand(1).getReg()));
+    if (MI.getNumOperands() == 3)
+      emitConstant(MI.getOperand(2).getImmedValue(), sizeOfPtr(Desc));
     break;
   }
   case X86II::MRMDestMem:
@@ -562,18 +566,10 @@ void Emitter::emitInstruction(MachineInstr &MI) {
   case X86II::MRMSrcReg:
     MCE.emitByte(BaseOpcode);
 
-    if (MI.getNumOperands() == 2) {
-      emitRegModRMByte(MI.getOperand(MI.getNumOperands()-1).getReg(),
-                       getX86RegNum(MI.getOperand(0).getReg()));
-    } else if (MI.getOperand(2).isImmediate()) {
-      emitRegModRMByte(MI.getOperand(1).getReg(),
-                       getX86RegNum(MI.getOperand(0).getReg()));
-
+    emitRegModRMByte(MI.getOperand(1).getReg(),
+                     getX86RegNum(MI.getOperand(0).getReg()));
+    if (MI.getNumOperands() == 3)
       emitConstant(MI.getOperand(2).getImmedValue(), sizeOfPtr(Desc));
-    } else {
-      emitRegModRMByte(MI.getOperand(2).getReg(),
-                       getX86RegNum(MI.getOperand(0).getReg()));
-    }
     break;
 
   case X86II::MRMSrcMem: