//
// The LLVM Compiler Infrastructure
//
-// This file was developed by the LLVM research group and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
//
//===----------------------------------------------------------------------===//
+#define DEBUG_TYPE "x86-emitter"
+#include "X86InstrInfo.h"
+#include "X86JITInfo.h"
+#include "X86Subtarget.h"
#include "X86TargetMachine.h"
#include "X86Relocations.h"
#include "X86.h"
#include "llvm/CodeGen/MachineCodeEmitter.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstr.h"
+#include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/Function.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/Support/Compiler.h"
+#include "llvm/Support/Debug.h"
#include "llvm/Target/TargetOptions.h"
-#include <iostream>
using namespace llvm;
-namespace {
- Statistic<>
- NumEmitted("x86-emitter", "Number of machine instructions emitted");
-}
+STATISTIC(NumEmitted, "Number of machine instructions emitted");
namespace {
class VISIBILITY_HIDDEN Emitter : public MachineFunctionPass {
const X86InstrInfo *II;
- TargetMachine &TM;
+ const TargetData *TD;
+ X86TargetMachine &TM;
MachineCodeEmitter &MCE;
+ intptr_t PICBaseOffset;
+ bool Is64BitMode;
+ bool IsPIC;
public:
- explicit Emitter(TargetMachine &tm, MachineCodeEmitter &mce)
- : II(0), TM(tm), MCE(mce) {}
- Emitter(TargetMachine &tm, MachineCodeEmitter &mce,
- const X86InstrInfo& ii)
- : II(&ii), TM(tm), MCE(mce) {}
+ static char ID;
+ explicit Emitter(X86TargetMachine &tm, MachineCodeEmitter &mce)
+ : MachineFunctionPass(&ID), II(0), TD(0), TM(tm),
+ MCE(mce), PICBaseOffset(0), Is64BitMode(false),
+ IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
+ Emitter(X86TargetMachine &tm, MachineCodeEmitter &mce,
+ const X86InstrInfo &ii, const TargetData &td, bool is64)
+ : MachineFunctionPass(&ID), II(&ii), TD(&td), TM(tm),
+ MCE(mce), PICBaseOffset(0), Is64BitMode(is64),
+ IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
bool runOnMachineFunction(MachineFunction &MF);
return "X86 Machine Code Emitter";
}
- void emitInstruction(const MachineInstr &MI);
+ void emitInstruction(const MachineInstr &MI,
+ const TargetInstrDesc *Desc);
+
+ void getAnalysisUsage(AnalysisUsage &AU) const {
+ AU.addRequired<MachineModuleInfo>();
+ MachineFunctionPass::getAnalysisUsage(AU);
+ }
private:
void emitPCRelativeBlockAddress(MachineBasicBlock *MBB);
- void emitPCRelativeValue(unsigned Address);
- void emitGlobalAddressForCall(GlobalValue *GV, bool isTailCall);
- void emitGlobalAddressForPtr(GlobalValue *GV, int Disp = 0);
- void emitExternalSymbolAddress(const char *ES, bool isPCRelative);
-
- void emitDisplacementField(const MachineOperand *RelocOp, int DispVal);
+ void emitGlobalAddress(GlobalValue *GV, unsigned Reloc,
+ intptr_t Disp = 0, intptr_t PCAdj = 0,
+ bool NeedStub = false, bool Indirect = false);
+ void emitExternalSymbolAddress(const char *ES, unsigned Reloc);
+ void emitConstPoolAddress(unsigned CPI, unsigned Reloc, intptr_t Disp = 0,
+ intptr_t PCAdj = 0);
+ void emitJumpTableAddress(unsigned JTI, unsigned Reloc,
+ intptr_t PCAdj = 0);
+
+ void emitDisplacementField(const MachineOperand *RelocOp, int DispVal,
+ intptr_t PCAdj = 0);
void emitRegModRMByte(unsigned ModRMReg, unsigned RegOpcodeField);
+ void emitRegModRMByte(unsigned RegOpcodeField);
void emitSIBByte(unsigned SS, unsigned Index, unsigned Base);
- void emitConstant(unsigned Val, unsigned Size);
+ void emitConstant(uint64_t Val, unsigned Size);
void emitMemModRMByte(const MachineInstr &MI,
- unsigned Op, unsigned RegOpcodeField);
+ unsigned Op, unsigned RegOpcodeField,
+ intptr_t PCAdj = 0);
+
+ unsigned getX86RegNum(unsigned RegNo) const;
+ bool gvNeedsNonLazyPtr(const GlobalValue *GV);
};
+ char Emitter::ID = 0;
}
/// createX86CodeEmitterPass - Return a pass that emits the collected X86 code
}
bool Emitter::runOnMachineFunction(MachineFunction &MF) {
- assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
- MF.getTarget().getRelocationModel() != Reloc::Static) &&
- "JIT relocation model must be set to static or default!");
- II = ((X86TargetMachine&)MF.getTarget()).getInstrInfo();
-
+
+ MCE.setModuleInfo(&getAnalysis<MachineModuleInfo>());
+
+ II = TM.getInstrInfo();
+ TD = TM.getTargetData();
+ Is64BitMode = TM.getSubtarget<X86Subtarget>().is64Bit();
+ IsPIC = TM.getRelocationModel() == Reloc::PIC_;
+
do {
+ DOUT << "JITTing function '" << MF.getFunction()->getName() << "'\n";
MCE.startFunction(MF);
for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
MBB != E; ++MBB) {
MCE.StartMachineBasicBlock(MBB);
for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
- I != E; ++I)
- emitInstruction(*I);
+ I != E; ++I) {
+ const TargetInstrDesc &Desc = I->getDesc();
+ emitInstruction(*I, &Desc);
+ // MOVPC32r is basically a call plus a pop instruction.
+ if (Desc.getOpcode() == X86::MOVPC32r)
+ emitInstruction(*I, &II->get(X86::POP32r));
+ NumEmitted++; // Keep track of the # of mi's emitted
+ }
}
} while (MCE.finishFunction(MF));
return false;
}
-/// emitPCRelativeValue - Emit a 32-bit PC relative address.
-///
-void Emitter::emitPCRelativeValue(unsigned Address) {
- MCE.emitWordLE(Address-MCE.getCurrentPCValue()-4);
-}
-
/// emitPCRelativeBlockAddress - This method keeps track of the information
/// necessary to resolve the address of this block later and emits a dummy
/// value.
MCE.emitWordLE(0);
}
-/// emitGlobalAddressForCall - Emit the specified address to the code stream
-/// assuming this is part of a function call, which is PC relative.
-///
-void Emitter::emitGlobalAddressForCall(GlobalValue *GV, bool isTailCall) {
- MCE.addRelocation(MachineRelocation::getGV(MCE.getCurrentPCOffset(),
- X86::reloc_pcrel_word, GV, 0,
- !isTailCall /*Doesn'tNeedStub*/));
- MCE.emitWordLE(0);
-}
-
/// emitGlobalAddress - Emit the specified address to the code stream assuming
-/// this is part of a "take the address of a global" instruction, which is not
-/// PC relative.
+/// this is part of a "take the address of a global" instruction.
///
-void Emitter::emitGlobalAddressForPtr(GlobalValue *GV, int Disp /* = 0 */) {
- MCE.addRelocation(MachineRelocation::getGV(MCE.getCurrentPCOffset(),
- X86::reloc_absolute_word, GV));
- MCE.emitWordLE(Disp); // The relocated value will be added to the displacement
+void Emitter::emitGlobalAddress(GlobalValue *GV, unsigned Reloc,
+ intptr_t Disp /* = 0 */,
+ intptr_t PCAdj /* = 0 */,
+ bool NeedStub /* = false */,
+ bool Indirect /* = false */) {
+ intptr_t RelocCST = 0;
+ if (Reloc == X86::reloc_picrel_word)
+ RelocCST = PICBaseOffset;
+ else if (Reloc == X86::reloc_pcrel_word)
+ RelocCST = PCAdj;
+ MachineRelocation MR = Indirect
+ ? MachineRelocation::getIndirectSymbol(MCE.getCurrentPCOffset(), Reloc,
+ GV, RelocCST, NeedStub)
+ : MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc,
+ GV, RelocCST, NeedStub);
+ MCE.addRelocation(MR);
+ // The relocated value will be added to the displacement
+ if (Reloc == X86::reloc_absolute_dword)
+ MCE.emitDWordLE(Disp);
+ else
+ MCE.emitWordLE((int32_t)Disp);
}
/// emitExternalSymbolAddress - Arrange for the address of an external symbol to
/// be emitted to the current location in the function, and allow it to be PC
/// relative.
-void Emitter::emitExternalSymbolAddress(const char *ES, bool isPCRelative) {
+void Emitter::emitExternalSymbolAddress(const char *ES, unsigned Reloc) {
+ intptr_t RelocCST = (Reloc == X86::reloc_picrel_word) ? PICBaseOffset : 0;
MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
- isPCRelative ? X86::reloc_pcrel_word : X86::reloc_absolute_word, ES));
- MCE.emitWordLE(0);
+ Reloc, ES, RelocCST));
+ if (Reloc == X86::reloc_absolute_dword)
+ MCE.emitDWordLE(0);
+ else
+ MCE.emitWordLE(0);
}
-/// N86 namespace - Native X86 Register numbers... used by X86 backend.
-///
-namespace N86 {
- enum {
- EAX = 0, ECX = 1, EDX = 2, EBX = 3, ESP = 4, EBP = 5, ESI = 6, EDI = 7
- };
+/// emitConstPoolAddress - Arrange for the address of an constant pool
+/// to be emitted to the current location in the function, and allow it to be PC
+/// relative.
+void Emitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc,
+ intptr_t Disp /* = 0 */,
+ intptr_t PCAdj /* = 0 */) {
+ intptr_t RelocCST = 0;
+ if (Reloc == X86::reloc_picrel_word)
+ RelocCST = PICBaseOffset;
+ else if (Reloc == X86::reloc_pcrel_word)
+ RelocCST = PCAdj;
+ MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
+ Reloc, CPI, RelocCST));
+ // The relocated value will be added to the displacement
+ if (Reloc == X86::reloc_absolute_dword)
+ MCE.emitDWordLE(Disp);
+ else
+ MCE.emitWordLE((int32_t)Disp);
}
+/// emitJumpTableAddress - Arrange for the address of a jump table to
+/// be emitted to the current location in the function, and allow it to be PC
+/// relative.
+void Emitter::emitJumpTableAddress(unsigned JTI, unsigned Reloc,
+ intptr_t PCAdj /* = 0 */) {
+ intptr_t RelocCST = 0;
+ if (Reloc == X86::reloc_picrel_word)
+ RelocCST = PICBaseOffset;
+ else if (Reloc == X86::reloc_pcrel_word)
+ RelocCST = PCAdj;
+ MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
+ Reloc, JTI, RelocCST));
+ // The relocated value will be added to the displacement
+ if (Reloc == X86::reloc_absolute_dword)
+ MCE.emitDWordLE(0);
+ else
+ MCE.emitWordLE(0);
+}
-// getX86RegNum - This function maps LLVM register identifiers to their X86
-// specific numbering, which is used in various places encoding instructions.
-//
-static unsigned getX86RegNum(unsigned RegNo) {
- switch(RegNo) {
- case X86::EAX: case X86::AX: case X86::AL: return N86::EAX;
- case X86::ECX: case X86::CX: case X86::CL: return N86::ECX;
- case X86::EDX: case X86::DX: case X86::DL: return N86::EDX;
- case X86::EBX: case X86::BX: case X86::BL: return N86::EBX;
- case X86::ESP: case X86::SP: case X86::AH: return N86::ESP;
- case X86::EBP: case X86::BP: case X86::CH: return N86::EBP;
- case X86::ESI: case X86::SI: case X86::DH: return N86::ESI;
- case X86::EDI: case X86::DI: case X86::BH: return N86::EDI;
-
- case X86::ST0: case X86::ST1: case X86::ST2: case X86::ST3:
- case X86::ST4: case X86::ST5: case X86::ST6: case X86::ST7:
- return RegNo-X86::ST0;
-
- case X86::XMM0: case X86::XMM1: case X86::XMM2: case X86::XMM3:
- case X86::XMM4: case X86::XMM5: case X86::XMM6: case X86::XMM7:
- return RegNo-X86::XMM0;
-
- default:
- assert(MRegisterInfo::isVirtualRegister(RegNo) &&
- "Unknown physical register!");
- assert(0 && "Register allocator hasn't allocated reg correctly yet!");
- return 0;
- }
+unsigned Emitter::getX86RegNum(unsigned RegNo) const {
+ return II->getRegisterInfo().getX86RegNum(RegNo);
}
inline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode,
MCE.emitByte(ModRMByte(3, RegOpcodeFld, getX86RegNum(ModRMReg)));
}
+void Emitter::emitRegModRMByte(unsigned RegOpcodeFld) {
+ MCE.emitByte(ModRMByte(3, RegOpcodeFld, 0));
+}
+
void Emitter::emitSIBByte(unsigned SS, unsigned Index, unsigned Base) {
// SIB byte is in the same format as the ModRMByte...
MCE.emitByte(ModRMByte(SS, Index, Base));
}
-void Emitter::emitConstant(unsigned Val, unsigned Size) {
+void Emitter::emitConstant(uint64_t Val, unsigned Size) {
// Output the constant in little endian byte order...
for (unsigned i = 0; i != Size; ++i) {
MCE.emitByte(Val & 255);
return Value == (signed char)Value;
}
+bool Emitter::gvNeedsNonLazyPtr(const GlobalValue *GV) {
+ // For Darwin, simulate the linktime GOT by using the same non-lazy-pointer
+ // mechanism as 32-bit mode.
+ return (!Is64BitMode || TM.getSubtarget<X86Subtarget>().isTargetDarwin()) &&
+ TM.getSubtarget<X86Subtarget>().GVRequiresExtraLoad(GV, TM, false);
+}
+
void Emitter::emitDisplacementField(const MachineOperand *RelocOp,
- int DispVal) {
+ int DispVal, intptr_t PCAdj) {
// If this is a simple integer displacement that doesn't require a relocation,
// emit it now.
if (!RelocOp) {
// Otherwise, this is something that requires a relocation. Emit it as such
// now.
- if (RelocOp->isGlobalAddress()) {
- emitGlobalAddressForPtr(RelocOp->getGlobal(), RelocOp->getOffset());
+ if (RelocOp->isGlobal()) {
+ // In 64-bit static small code model, we could potentially emit absolute.
+ // But it's probably not beneficial.
+ // 89 05 00 00 00 00 mov %eax,0(%rip) # PC-relative
+ // 89 04 25 00 00 00 00 mov %eax,0x0 # Absolute
+ unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
+ : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
+ bool NeedStub = isa<Function>(RelocOp->getGlobal());
+ bool Indirect = gvNeedsNonLazyPtr(RelocOp->getGlobal());
+ emitGlobalAddress(RelocOp->getGlobal(), rt, RelocOp->getOffset(),
+ PCAdj, NeedStub, Indirect);
+ } else if (RelocOp->isCPI()) {
+ unsigned rt = Is64BitMode ? X86::reloc_pcrel_word : X86::reloc_picrel_word;
+ emitConstPoolAddress(RelocOp->getIndex(), rt,
+ RelocOp->getOffset(), PCAdj);
+ } else if (RelocOp->isJTI()) {
+ unsigned rt = Is64BitMode ? X86::reloc_pcrel_word : X86::reloc_picrel_word;
+ emitJumpTableAddress(RelocOp->getIndex(), rt, PCAdj);
} else {
assert(0 && "Unknown value to relocate!");
}
}
void Emitter::emitMemModRMByte(const MachineInstr &MI,
- unsigned Op, unsigned RegOpcodeField) {
+ unsigned Op, unsigned RegOpcodeField,
+ intptr_t PCAdj) {
const MachineOperand &Op3 = MI.getOperand(Op+3);
int DispVal = 0;
const MachineOperand *DispForReloc = 0;
// Figure out what sort of displacement we have to handle here.
- if (Op3.isGlobalAddress()) {
+ if (Op3.isGlobal()) {
DispForReloc = &Op3;
- } else if (Op3.isConstantPoolIndex()) {
- DispVal += MCE.getConstantPoolEntryAddress(Op3.getConstantPoolIndex());
- DispVal += Op3.getOffset();
- } else if (Op3.isJumpTableIndex()) {
- DispVal += MCE.getJumpTableEntryAddress(Op3.getJumpTableIndex());
+ } else if (Op3.isCPI()) {
+ if (Is64BitMode || IsPIC) {
+ DispForReloc = &Op3;
+ } else {
+ DispVal += MCE.getConstantPoolEntryAddress(Op3.getIndex());
+ DispVal += Op3.getOffset();
+ }
+ } else if (Op3.isJTI()) {
+ if (Is64BitMode || IsPIC) {
+ DispForReloc = &Op3;
+ } else {
+ DispVal += MCE.getJumpTableEntryAddress(Op3.getIndex());
+ }
} else {
DispVal = Op3.getImm();
}
unsigned BaseReg = Base.getReg();
// Is a SIB byte needed?
- if (IndexReg.getReg() == 0 && BaseReg != X86::ESP) {
+ if ((!Is64BitMode || DispForReloc) && IndexReg.getReg() == 0 &&
+ (BaseReg == 0 || getX86RegNum(BaseReg) != N86::ESP)) {
if (BaseReg == 0) { // Just a displacement?
// Emit special case [disp32] encoding
MCE.emitByte(ModRMByte(0, RegOpcodeField, 5));
- emitDisplacementField(DispForReloc, DispVal);
+ emitDisplacementField(DispForReloc, DispVal, PCAdj);
} else {
unsigned BaseRegNo = getX86RegNum(BaseReg);
if (!DispForReloc && DispVal == 0 && BaseRegNo != N86::EBP) {
} else {
// Emit the most general non-SIB encoding: [REG+disp32]
MCE.emitByte(ModRMByte(2, RegOpcodeField, BaseRegNo));
- emitDisplacementField(DispForReloc, DispVal);
+ emitDisplacementField(DispForReloc, DispVal, PCAdj);
}
}
} else { // We need a SIB byte, so start by outputting the ModR/M byte first
- assert(IndexReg.getReg() != X86::ESP && "Cannot use ESP as index reg!");
+ assert(IndexReg.getReg() != X86::ESP &&
+ IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!");
bool ForceDisp32 = false;
bool ForceDisp8 = false;
// Emit the normal disp32 encoding.
MCE.emitByte(ModRMByte(2, RegOpcodeField, 4));
ForceDisp32 = true;
- } else if (DispVal == 0 && BaseReg != X86::EBP) {
+ } else if (DispVal == 0 && getX86RegNum(BaseReg) != N86::EBP) {
// Emit no displacement ModR/M byte
MCE.emitByte(ModRMByte(0, RegOpcodeField, 4));
} else if (isDisp8(DispVal)) {
if (BaseReg == 0) {
// Handle the SIB byte for the case where there is no base. The
// displacement has already been output.
- assert(IndexReg.getReg() && "Index register must be specified!");
- emitSIBByte(SS, getX86RegNum(IndexReg.getReg()), 5);
+ unsigned IndexRegNo;
+ if (IndexReg.getReg())
+ IndexRegNo = getX86RegNum(IndexReg.getReg());
+ else
+ IndexRegNo = 4; // For example [ESP+1*<noreg>+4]
+ emitSIBByte(SS, IndexRegNo, 5);
} else {
unsigned BaseRegNo = getX86RegNum(BaseReg);
unsigned IndexRegNo;
if (ForceDisp8) {
emitConstant(DispVal, 1);
} else if (DispVal != 0 || ForceDisp32) {
- emitDisplacementField(DispForReloc, DispVal);
+ emitDisplacementField(DispForReloc, DispVal, PCAdj);
}
}
}
-static unsigned sizeOfImm(const TargetInstrDescriptor &Desc) {
- switch (Desc.TSFlags & X86II::ImmMask) {
- case X86II::Imm8: return 1;
- case X86II::Imm16: return 2;
- case X86II::Imm32: return 4;
- default: assert(0 && "Immediate size not set!");
- return 0;
- }
-}
+void Emitter::emitInstruction(const MachineInstr &MI,
+ const TargetInstrDesc *Desc) {
+ DOUT << MI;
+
+ unsigned Opcode = Desc->Opcode;
-void Emitter::emitInstruction(const MachineInstr &MI) {
- NumEmitted++; // Keep track of the # of mi's emitted
+ // Emit the lock opcode prefix as needed.
+ if (Desc->TSFlags & X86II::LOCK) MCE.emitByte(0xF0);
- unsigned Opcode = MI.getOpcode();
- const TargetInstrDescriptor &Desc = II->get(Opcode);
+ // Emit segment override opcode prefix as needed.
+ switch (Desc->TSFlags & X86II::SegOvrMask) {
+ case X86II::FS:
+ MCE.emitByte(0x64);
+ break;
+ case X86II::GS:
+ MCE.emitByte(0x65);
+ break;
+ default: assert(0 && "Invalid segment!");
+ case 0: break; // No segment override!
+ }
// Emit the repeat opcode prefix as needed.
- if ((Desc.TSFlags & X86II::Op0Mask) == X86II::REP) MCE.emitByte(0xF3);
+ if ((Desc->TSFlags & X86II::Op0Mask) == X86II::REP) MCE.emitByte(0xF3);
// Emit the operand size opcode prefix as needed.
- if (Desc.TSFlags & X86II::OpSize) MCE.emitByte(0x66);
+ if (Desc->TSFlags & X86II::OpSize) MCE.emitByte(0x66);
- switch (Desc.TSFlags & X86II::Op0Mask) {
- case X86II::TB:
- MCE.emitByte(0x0F); // Two-byte opcode prefix
+ // Emit the address size opcode prefix as needed.
+ if (Desc->TSFlags & X86II::AdSize) MCE.emitByte(0x67);
+
+ bool Need0FPrefix = false;
+ switch (Desc->TSFlags & X86II::Op0Mask) {
+ case X86II::TB: // Two-byte opcode prefix
+ case X86II::T8: // 0F 38
+ case X86II::TA: // 0F 3A
+ Need0FPrefix = true;
break;
case X86II::REP: break; // already handled.
case X86II::XS: // F3 0F
MCE.emitByte(0xF3);
- MCE.emitByte(0x0F);
+ Need0FPrefix = true;
break;
case X86II::XD: // F2 0F
MCE.emitByte(0xF2);
- MCE.emitByte(0x0F);
+ Need0FPrefix = true;
break;
case X86II::D8: case X86II::D9: case X86II::DA: case X86II::DB:
case X86II::DC: case X86II::DD: case X86II::DE: case X86II::DF:
MCE.emitByte(0xD8+
- (((Desc.TSFlags & X86II::Op0Mask)-X86II::D8)
+ (((Desc->TSFlags & X86II::Op0Mask)-X86II::D8)
>> X86II::Op0Shift));
break; // Two-byte opcode prefix
default: assert(0 && "Invalid prefix!");
case 0: break; // No prefix!
}
+ if (Is64BitMode) {
+ // REX prefix
+ unsigned REX = X86InstrInfo::determineREX(MI);
+ if (REX)
+ MCE.emitByte(0x40 | REX);
+ }
+
+ // 0x0F escape code must be emitted just before the opcode.
+ if (Need0FPrefix)
+ MCE.emitByte(0x0F);
+
+ switch (Desc->TSFlags & X86II::Op0Mask) {
+ case X86II::T8: // 0F 38
+ MCE.emitByte(0x38);
+ break;
+ case X86II::TA: // 0F 3A
+ MCE.emitByte(0x3A);
+ break;
+ }
+
// If this is a two-address instruction, skip one of the register operands.
+ unsigned NumOps = Desc->getNumOperands();
unsigned CurOp = 0;
- CurOp += (Desc.Flags & M_2_ADDR_FLAG) != 0;
-
- unsigned char BaseOpcode = II->getBaseOpcodeFor(Opcode);
- switch (Desc.TSFlags & X86II::FormMask) {
+ if (NumOps > 1 && Desc->getOperandConstraint(1, TOI::TIED_TO) != -1)
+ ++CurOp;
+ else if (NumOps > 2 && Desc->getOperandConstraint(NumOps-1, TOI::TIED_TO)== 0)
+ // Skip the last source operand that is tied_to the dest reg. e.g. LXADD32
+ --NumOps;
+
+ unsigned char BaseOpcode = II->getBaseOpcodeFor(Desc);
+ switch (Desc->TSFlags & X86II::FormMask) {
default: assert(0 && "Unknown FormMask value in X86 MachineCodeEmitter!");
case X86II::Pseudo:
-#ifndef NDEBUG
+ // Remember the current PC offset, this is the PIC relocation
+ // base address.
switch (Opcode) {
default:
assert(0 && "psuedo instructions should be removed before code emission");
- case TargetInstrInfo::INLINEASM:
- std::cerr << "JIT does not support inline asm!\n";
- abort();
- case X86::IMPLICIT_USE:
- case X86::IMPLICIT_DEF:
- case X86::IMPLICIT_DEF_GR8:
- case X86::IMPLICIT_DEF_GR16:
- case X86::IMPLICIT_DEF_GR32:
- case X86::IMPLICIT_DEF_FR32:
- case X86::IMPLICIT_DEF_FR64:
- case X86::IMPLICIT_DEF_VR64:
- case X86::IMPLICIT_DEF_VR128:
+ break;
+ case TargetInstrInfo::INLINEASM: {
+ // We allow inline assembler nodes with empty bodies - they can
+ // implicitly define registers, which is ok for JIT.
+ if (MI.getOperand(0).getSymbolName()[0]) {
+ assert(0 && "JIT does not support inline asm!\n");
+ abort();
+ }
+ break;
+ }
+ case TargetInstrInfo::DBG_LABEL:
+ case TargetInstrInfo::EH_LABEL:
+ MCE.emitLabel(MI.getOperand(0).getImm());
+ break;
+ case TargetInstrInfo::IMPLICIT_DEF:
+ case TargetInstrInfo::DECLARE:
+ case X86::DWARF_LOC:
case X86::FP_REG_KILL:
break;
+ case X86::TLS_tp: {
+ MCE.emitByte(BaseOpcode);
+ unsigned RegOpcodeField = getX86RegNum(MI.getOperand(0).getReg());
+ MCE.emitByte(ModRMByte(0, RegOpcodeField, 5));
+ emitConstant(0, 4);
+ break;
+ }
+ case X86::TLS_gs_ri: {
+ MCE.emitByte(BaseOpcode);
+ unsigned RegOpcodeField = getX86RegNum(MI.getOperand(0).getReg());
+ MCE.emitByte(ModRMByte(0, RegOpcodeField, 5));
+ GlobalValue* GV = MI.getOperand(1).getGlobal();
+ unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
+ : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
+ emitGlobalAddress(GV, rt);
+ break;
+ }
+ case X86::MOVPC32r: {
+ // This emits the "call" portion of this pseudo instruction.
+ MCE.emitByte(BaseOpcode);
+ emitConstant(0, X86InstrInfo::sizeOfImm(Desc));
+ // Remember PIC base.
+ PICBaseOffset = (intptr_t) MCE.getCurrentPCOffset();
+ X86JITInfo *JTI = TM.getJITInfo();
+ JTI->setPICBase(MCE.getCurrentPCValue());
+ break;
+ }
}
-#endif
- CurOp = MI.getNumOperands();
+ CurOp = NumOps;
break;
-
case X86II::RawFrm:
MCE.emitByte(BaseOpcode);
- if (CurOp != MI.getNumOperands()) {
+
+ if (CurOp != NumOps) {
const MachineOperand &MO = MI.getOperand(CurOp++);
- if (MO.isMachineBasicBlock()) {
- emitPCRelativeBlockAddress(MO.getMachineBasicBlock());
- } else if (MO.isGlobalAddress()) {
- bool isTailCall = Opcode == X86::TAILJMPd ||
- Opcode == X86::TAILJMPr || Opcode == X86::TAILJMPm;
- emitGlobalAddressForCall(MO.getGlobal(), isTailCall);
- } else if (MO.isExternalSymbol()) {
- emitExternalSymbolAddress(MO.getSymbolName(), true);
- } else if (MO.isImmediate()) {
- emitConstant(MO.getImm(), sizeOfImm(Desc));
+
+ DOUT << "RawFrm CurOp " << CurOp << "\n";
+ DOUT << "isMBB " << MO.isMBB() << "\n";
+ DOUT << "isGlobal " << MO.isGlobal() << "\n";
+ DOUT << "isSymbol " << MO.isSymbol() << "\n";
+ DOUT << "isImm " << MO.isImm() << "\n";
+
+ if (MO.isMBB()) {
+ emitPCRelativeBlockAddress(MO.getMBB());
+ } else if (MO.isGlobal()) {
+ // Assume undefined functions may be outside the Small codespace.
+ bool NeedStub =
+ (Is64BitMode &&
+ (TM.getCodeModel() == CodeModel::Large ||
+ TM.getSubtarget<X86Subtarget>().isTargetDarwin())) ||
+ Opcode == X86::TAILJMPd;
+ emitGlobalAddress(MO.getGlobal(), X86::reloc_pcrel_word,
+ MO.getOffset(), 0, NeedStub);
+ } else if (MO.isSymbol()) {
+ emitExternalSymbolAddress(MO.getSymbolName(), X86::reloc_pcrel_word);
+ } else if (MO.isImm()) {
+ if (Opcode == X86::CALLpcrel32 || Opcode == X86::CALL64pcrel32) {
+ // Fix up immediate operand for pc relative calls.
+ intptr_t Imm = (intptr_t)MO.getImm();
+ Imm = Imm - MCE.getCurrentPCValue() - 4;
+ emitConstant(Imm, X86InstrInfo::sizeOfImm(Desc));
+ } else
+ emitConstant(MO.getImm(), X86InstrInfo::sizeOfImm(Desc));
} else {
assert(0 && "Unknown RawFrm operand!");
}
case X86II::AddRegFrm:
MCE.emitByte(BaseOpcode + getX86RegNum(MI.getOperand(CurOp++).getReg()));
- if (CurOp != MI.getNumOperands()) {
+ if (CurOp != NumOps) {
const MachineOperand &MO1 = MI.getOperand(CurOp++);
- if (MO1.isGlobalAddress()) {
- assert(sizeOfImm(Desc) == 4 &&
- "Don't know how to emit non-pointer values!");
- emitGlobalAddressForPtr(MO1.getGlobal(), MO1.getOffset());
- } else if (MO1.isExternalSymbol()) {
- assert(sizeOfImm(Desc) == 4 &&
- "Don't know how to emit non-pointer values!");
- emitExternalSymbolAddress(MO1.getSymbolName(), false);
- } else if (MO1.isJumpTableIndex()) {
- assert(sizeOfImm(Desc) == 4 &&
- "Don't know how to emit non-pointer values!");
- emitConstant(MCE.getJumpTableEntryAddress(MO1.getJumpTableIndex()), 4);
- } else {
- emitConstant(MO1.getImm(), sizeOfImm(Desc));
+ unsigned Size = X86InstrInfo::sizeOfImm(Desc);
+ if (MO1.isImm())
+ emitConstant(MO1.getImm(), Size);
+ else {
+ unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
+ : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
+ // This should not occur on Darwin for relocatable objects.
+ if (Opcode == X86::MOV64ri)
+ rt = X86::reloc_absolute_dword; // FIXME: add X86II flag?
+ if (MO1.isGlobal()) {
+ bool NeedStub = isa<Function>(MO1.getGlobal());
+ bool Indirect = gvNeedsNonLazyPtr(MO1.getGlobal());
+ emitGlobalAddress(MO1.getGlobal(), rt, MO1.getOffset(), 0,
+ NeedStub, Indirect);
+ } else if (MO1.isSymbol())
+ emitExternalSymbolAddress(MO1.getSymbolName(), rt);
+ else if (MO1.isCPI())
+ emitConstPoolAddress(MO1.getIndex(), rt);
+ else if (MO1.isJTI())
+ emitJumpTableAddress(MO1.getIndex(), rt);
}
}
break;
emitRegModRMByte(MI.getOperand(CurOp).getReg(),
getX86RegNum(MI.getOperand(CurOp+1).getReg()));
CurOp += 2;
- if (CurOp != MI.getNumOperands())
- emitConstant(MI.getOperand(CurOp++).getImm(), sizeOfImm(Desc));
+ if (CurOp != NumOps)
+ emitConstant(MI.getOperand(CurOp++).getImm(), X86InstrInfo::sizeOfImm(Desc));
break;
}
- case X86II::MRMDestMem:
+ case X86II::MRMDestMem: {
MCE.emitByte(BaseOpcode);
emitMemModRMByte(MI, CurOp, getX86RegNum(MI.getOperand(CurOp+4).getReg()));
CurOp += 5;
- if (CurOp != MI.getNumOperands())
- emitConstant(MI.getOperand(CurOp++).getImm(), sizeOfImm(Desc));
+ if (CurOp != NumOps)
+ emitConstant(MI.getOperand(CurOp++).getImm(), X86InstrInfo::sizeOfImm(Desc));
break;
+ }
case X86II::MRMSrcReg:
MCE.emitByte(BaseOpcode);
emitRegModRMByte(MI.getOperand(CurOp+1).getReg(),
getX86RegNum(MI.getOperand(CurOp).getReg()));
CurOp += 2;
- if (CurOp != MI.getNumOperands())
- emitConstant(MI.getOperand(CurOp++).getImm(), sizeOfImm(Desc));
+ if (CurOp != NumOps)
+ emitConstant(MI.getOperand(CurOp++).getImm(), X86InstrInfo::sizeOfImm(Desc));
break;
- case X86II::MRMSrcMem:
+ case X86II::MRMSrcMem: {
+ intptr_t PCAdj = (CurOp+5 != NumOps) ? X86InstrInfo::sizeOfImm(Desc) : 0;
+
MCE.emitByte(BaseOpcode);
- emitMemModRMByte(MI, CurOp+1, getX86RegNum(MI.getOperand(CurOp).getReg()));
+ emitMemModRMByte(MI, CurOp+1, getX86RegNum(MI.getOperand(CurOp).getReg()),
+ PCAdj);
CurOp += 5;
- if (CurOp != MI.getNumOperands())
- emitConstant(MI.getOperand(CurOp++).getImm(), sizeOfImm(Desc));
+ if (CurOp != NumOps)
+ emitConstant(MI.getOperand(CurOp++).getImm(), X86InstrInfo::sizeOfImm(Desc));
break;
+ }
case X86II::MRM0r: case X86II::MRM1r:
case X86II::MRM2r: case X86II::MRM3r:
case X86II::MRM4r: case X86II::MRM5r:
- case X86II::MRM6r: case X86II::MRM7r:
+ case X86II::MRM6r: case X86II::MRM7r: {
MCE.emitByte(BaseOpcode);
- emitRegModRMByte(MI.getOperand(CurOp++).getReg(),
- (Desc.TSFlags & X86II::FormMask)-X86II::MRM0r);
- if (CurOp != MI.getNumOperands())
- emitConstant(MI.getOperand(CurOp++).getImm(), sizeOfImm(Desc));
+ // Special handling of lfence and mfence.
+ if (Desc->getOpcode() == X86::LFENCE ||
+ Desc->getOpcode() == X86::MFENCE)
+ emitRegModRMByte((Desc->TSFlags & X86II::FormMask)-X86II::MRM0r);
+ else
+ emitRegModRMByte(MI.getOperand(CurOp++).getReg(),
+ (Desc->TSFlags & X86II::FormMask)-X86II::MRM0r);
+
+ if (CurOp != NumOps) {
+ const MachineOperand &MO1 = MI.getOperand(CurOp++);
+ unsigned Size = X86InstrInfo::sizeOfImm(Desc);
+ if (MO1.isImm())
+ emitConstant(MO1.getImm(), Size);
+ else {
+ unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
+ : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
+ if (Opcode == X86::MOV64ri32)
+ rt = X86::reloc_absolute_word; // FIXME: add X86II flag?
+ if (MO1.isGlobal()) {
+ bool NeedStub = isa<Function>(MO1.getGlobal());
+ bool Indirect = gvNeedsNonLazyPtr(MO1.getGlobal());
+ emitGlobalAddress(MO1.getGlobal(), rt, MO1.getOffset(), 0,
+ NeedStub, Indirect);
+ } else if (MO1.isSymbol())
+ emitExternalSymbolAddress(MO1.getSymbolName(), rt);
+ else if (MO1.isCPI())
+ emitConstPoolAddress(MO1.getIndex(), rt);
+ else if (MO1.isJTI())
+ emitJumpTableAddress(MO1.getIndex(), rt);
+ }
+ }
break;
+ }
case X86II::MRM0m: case X86II::MRM1m:
case X86II::MRM2m: case X86II::MRM3m:
case X86II::MRM4m: case X86II::MRM5m:
- case X86II::MRM6m: case X86II::MRM7m:
+ case X86II::MRM6m: case X86II::MRM7m: {
+ intptr_t PCAdj = (CurOp+4 != NumOps) ?
+ (MI.getOperand(CurOp+4).isImm() ? X86InstrInfo::sizeOfImm(Desc) : 4) : 0;
+
MCE.emitByte(BaseOpcode);
- emitMemModRMByte(MI, CurOp, (Desc.TSFlags & X86II::FormMask)-X86II::MRM0m);
+ emitMemModRMByte(MI, CurOp, (Desc->TSFlags & X86II::FormMask)-X86II::MRM0m,
+ PCAdj);
CurOp += 4;
- if (CurOp != MI.getNumOperands()) {
+ if (CurOp != NumOps) {
const MachineOperand &MO = MI.getOperand(CurOp++);
- if (MO.isImmediate())
- emitConstant(MO.getImm(), sizeOfImm(Desc));
- else if (MO.isGlobalAddress())
- emitGlobalAddressForPtr(MO.getGlobal(), MO.getOffset());
- else if (MO.isJumpTableIndex())
- emitConstant(MCE.getJumpTableEntryAddress(MO.getJumpTableIndex()), 4);
- else
- assert(0 && "Unknown operand!");
+ unsigned Size = X86InstrInfo::sizeOfImm(Desc);
+ if (MO.isImm())
+ emitConstant(MO.getImm(), Size);
+ else {
+ unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
+ : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
+ if (Opcode == X86::MOV64mi32)
+ rt = X86::reloc_absolute_word; // FIXME: add X86II flag?
+ if (MO.isGlobal()) {
+ bool NeedStub = isa<Function>(MO.getGlobal());
+ bool Indirect = gvNeedsNonLazyPtr(MO.getGlobal());
+ emitGlobalAddress(MO.getGlobal(), rt, MO.getOffset(), 0,
+ NeedStub, Indirect);
+ } else if (MO.isSymbol())
+ emitExternalSymbolAddress(MO.getSymbolName(), rt);
+ else if (MO.isCPI())
+ emitConstPoolAddress(MO.getIndex(), rt);
+ else if (MO.isJTI())
+ emitJumpTableAddress(MO.getIndex(), rt);
+ }
}
break;
+ }
case X86II::MRMInitReg:
MCE.emitByte(BaseOpcode);
break;
}
- if ((Desc.Flags & M_VARIABLE_OPS) == 0)
- assert(CurOp == MI.getNumOperands() && "Unknown encoding!");
+ if (!Desc->isVariadic() && CurOp != NumOps) {
+ cerr << "Cannot encode: ";
+ MI.dump();
+ cerr << '\n';
+ abort();
+ }
}
projects / oota-llvm.git / blobdiff