Turn off the old way of handling debug information in the code generator. Use

[oota-llvm.git] / lib / Target / X86 / X86FastISel.cpp

diff --git a/lib/Target/X86/X86FastISel.cpp b/lib/Target/X86/X86FastISel.cpp
index 3056e39c917bc26dc0d700187185896f7a4a1b98..d85d2fbea3fcfb18d87e699ec48ae42140569147 100644 (file)
--- a/lib/Target/X86/X86FastISel.cpp
+++ b/lib/Target/X86/X86FastISel.cpp
@@ -51,6 +51,7 @@ class X86FastISel : public FastISel {
 public:
   explicit X86FastISel(MachineFunction &mf,
                        MachineModuleInfo *mmi,
+                       DwarfWriter *dw,
                        DenseMap<const Value *, unsigned> &vm,
                        DenseMap<const BasicBlock *, MachineBasicBlock *> &bm,
                        DenseMap<const AllocaInst *, int> &am
@@ -58,7 +59,7 @@ public:
                        , SmallSet<Instruction*, 8> &cil
 #endif
                        )
-    : FastISel(mf, mmi, vm, bm, am
+    : FastISel(mf, mmi, dw, vm, bm, am
 #ifndef NDEBUG
                , cil
 #endif
@@ -386,7 +387,7 @@ bool X86FastISel::X86SelectAddress(Value *V, X86AddressMode &AM, bool isCall) {
         unsigned Idx = cast<ConstantInt>(Op)->getZExtValue();
         Disp += SL->getElementOffset(Idx);
       } else {
-        uint64_t S = TD.getABITypeSize(GTI.getIndexedType());
+        uint64_t S = TD.getTypePaddedSize(GTI.getIndexedType());
         if (ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
           // Constant-offset addressing.
           Disp += CI->getSExtValue() * S;
@@ -758,11 +759,11 @@ bool X86FastISel::X86SelectBranch(Instruction *I) {
     //   %obit = extractvalue { i32, i1 } %t, 1
     //   br i1 %obit, label %overflow, label %normal
     //
-    // The %sum and %obit are converted in an ADD and a SETO/SETC before
+    // The %sum and %obit are converted in an ADD and a SETO/SETB before
     // reaching the branch. Therefore, we search backwards through the MBB
-    // looking for the SETO/SETC instruction. If an instruction modifies the
-    // EFLAGS register before we reach the SETO/SETC instruction, then we can't
-    // convert the branch into a JO/JC instruction.
+    // looking for the SETO/SETB instruction. If an instruction modifies the
+    // EFLAGS register before we reach the SETO/SETB instruction, then we can't
+    // convert the branch into a JO/JB instruction.
 
     Value *Agg = EI->getAggregateOperand();
 
@@ -782,9 +783,9 @@ bool X86FastISel::X86SelectBranch(Instruction *I) {
             const MachineInstr &MI = *RI;
 
             if (MI.modifiesRegister(Reg)) {
-              unsigned Src, Dst;
+              unsigned Src, Dst, SrcSR, DstSR;
 
-              if (getInstrInfo()->isMoveInstr(MI, Src, Dst)) {
+              if (getInstrInfo()->isMoveInstr(MI, Src, Dst, SrcSR, DstSR)) {
                 Reg = Src;
                 continue;
               }
@@ -814,9 +815,9 @@ bool X86FastISel::X86SelectBranch(Instruction *I) {
           if (SetMI) {
             unsigned OpCode = SetMI->getOpcode();
 
-            if (OpCode == X86::SETOr || OpCode == X86::SETCr) {
+            if (OpCode == X86::SETOr || OpCode == X86::SETBr) {
               BuildMI(MBB, TII.get((OpCode == X86::SETOr) ? 
-                                   X86::JO : X86::JC)).addMBB(TrueMBB);
+                                   X86::JO : X86::JB)).addMBB(TrueMBB);
               FastEmitBranch(FalseMBB);
               MBB->addSuccessor(TrueMBB);
               return true;
@@ -1010,7 +1011,8 @@ bool X86FastISel::X86SelectTrunc(Instruction *I) {
   BuildMI(MBB, TII.get(CopyOpc), CopyReg).addReg(InputReg);
 
   // Then issue an extract_subreg.
-  unsigned ResultReg = FastEmitInst_extractsubreg(CopyReg, X86::SUBREG_8BIT);
+  unsigned ResultReg = FastEmitInst_extractsubreg(DstVT.getSimpleVT(),
+                                                  CopyReg, X86::SUBREG_8BIT);
   if (!ResultReg)
     return false;
 
@@ -1086,7 +1088,7 @@ bool X86FastISel::X86VisitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
 
     ResultReg = createResultReg(TLI.getRegClassFor(MVT::i8));
     BuildMI(MBB, TII.get((Intrinsic == Intrinsic::sadd_with_overflow) ?
-                         X86::SETOr : X86::SETCr), ResultReg);
+                         X86::SETOr : X86::SETBr), ResultReg);
     return true;
   }
   }
@@ -1469,7 +1471,7 @@ unsigned X86FastISel::TargetMaterializeConstant(Constant *C) {
   unsigned Align = TD.getPreferredTypeAlignmentShift(C->getType());
   if (Align == 0) {
     // Alignment of vector types.  FIXME!
-    Align = TD.getABITypeSize(C->getType());
+    Align = TD.getTypePaddedSize(C->getType());
     Align = Log2_64(Align);
   }
   
@@ -1512,6 +1514,7 @@ unsigned X86FastISel::TargetMaterializeAlloca(AllocaInst *C) {
 namespace llvm {
   llvm::FastISel *X86::createFastISel(MachineFunction &mf,
                         MachineModuleInfo *mmi,
+                        DwarfWriter *dw,
                         DenseMap<const Value *, unsigned> &vm,
                         DenseMap<const BasicBlock *, MachineBasicBlock *> &bm,
                         DenseMap<const AllocaInst *, int> &am
@@ -1519,7 +1522,7 @@ namespace llvm {
                         , SmallSet<Instruction*, 8> &cil
 #endif
                         ) {
-    return new X86FastISel(mf, mmi, vm, bm, am
+    return new X86FastISel(mf, mmi, dw, vm, bm, am
 #ifndef NDEBUG
                            , cil
 #endif