#include "llvm/CallingConv.h"
#include "llvm/DerivedTypes.h"
#include "llvm/Instructions.h"
+#include "llvm/Intrinsics.h"
#include "llvm/CodeGen/FastISel.h"
#include "llvm/CodeGen/MachineConstantPool.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
public:
explicit X86FastISel(MachineFunction &mf,
+ MachineModuleInfo *mmi,
+ DwarfWriter *dw,
DenseMap<const Value *, unsigned> &vm,
DenseMap<const BasicBlock *, MachineBasicBlock *> &bm,
- DenseMap<const AllocaInst *, int> &am)
- : FastISel(mf, vm, bm, am) {
+ DenseMap<const AllocaInst *, int> &am
+#ifndef NDEBUG
+ , SmallSet<Instruction*, 8> &cil
+#endif
+ )
+ : FastISel(mf, mmi, dw, vm, bm, am
+#ifndef NDEBUG
+ , cil
+#endif
+ ) {
Subtarget = &TM.getSubtarget<X86Subtarget>();
StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
X86ScalarSSEf64 = Subtarget->hasSSE2();
#include "X86GenFastISel.inc"
private:
+ bool X86FastEmitCompare(Value *LHS, Value *RHS, MVT VT);
+
bool X86FastEmitLoad(MVT VT, const X86AddressMode &AM, unsigned &RR);
+ bool X86FastEmitStore(MVT VT, Value *Val,
+ const X86AddressMode &AM);
bool X86FastEmitStore(MVT VT, unsigned Val,
const X86AddressMode &AM);
bool X86SelectSelect(Instruction *I);
bool X86SelectTrunc(Instruction *I);
-
+
bool X86SelectFPExt(Instruction *I);
bool X86SelectFPTrunc(Instruction *I);
+ bool X86SelectExtractValue(Instruction *I);
+
+ bool X86VisitIntrinsicCall(CallInst &I, unsigned Intrinsic);
bool X86SelectCall(Instruction *I);
CCAssignFn *CCAssignFnForCall(unsigned CC, bool isTailCall = false);
+ const X86InstrInfo *getInstrInfo() const {
+ return getTargetMachine()->getInstrInfo();
+ }
+ const X86TargetMachine *getTargetMachine() const {
+ return static_cast<const X86TargetMachine *>(&TM);
+ }
+
unsigned TargetMaterializeConstant(Constant *C);
unsigned TargetMaterializeAlloca(AllocaInst *C);
(VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1
}
+ bool isTypeLegal(const Type *Ty, MVT &VT, bool AllowI1 = false);
};
-static bool isTypeLegal(const Type *Ty, const TargetLowering &TLI, MVT &VT,
- bool AllowI1 = false) {
- VT = MVT::getMVT(Ty, /*HandleUnknown=*/true);
+bool X86FastISel::isTypeLegal(const Type *Ty, MVT &VT, bool AllowI1) {
+ VT = TLI.getValueType(Ty, /*HandleUnknown=*/true);
if (VT == MVT::Other || !VT.isSimple())
// Unhandled type. Halt "fast" selection and bail.
return false;
- if (VT == MVT::iPTR)
- // Use pointer type.
- VT = TLI.getPointerTy();
+
+ // For now, require SSE/SSE2 for performing floating-point operations,
+ // since x87 requires additional work.
+ if (VT == MVT::f64 && !X86ScalarSSEf64)
+ return false;
+ if (VT == MVT::f32 && !X86ScalarSSEf32)
+ return false;
+ // Similarly, no f80 support yet.
+ if (VT == MVT::f80)
+ return false;
// We only handle legal types. For example, on x86-32 the instruction
// selector contains all of the 64-bit instructions from x86-64,
// under the assumption that i64 won't be used if the target doesn't
if (CC == CallingConv::X86_FastCall)
return CC_X86_32_FastCall;
- else if (CC == CallingConv::Fast && isTaillCall)
- return CC_X86_32_TailCall;
else if (CC == CallingConv::Fast)
return CC_X86_32_FastCC;
else
}
break;
case MVT::f80:
- Opc = X86::LD_Fp80m;
- RC = X86::RFP80RegisterClass;
- break;
+ // No f80 support yet.
+ return false;
}
ResultReg = createResultReg(RC);
const X86AddressMode &AM) {
// Get opcode and regclass of the output for the given store instruction.
unsigned Opc = 0;
- const TargetRegisterClass *RC = NULL;
switch (VT.getSimpleVT()) {
+ case MVT::f80: // No f80 support yet.
default: return false;
- case MVT::i8:
- Opc = X86::MOV8mr;
- RC = X86::GR8RegisterClass;
- break;
- case MVT::i16:
- Opc = X86::MOV16mr;
- RC = X86::GR16RegisterClass;
- break;
- case MVT::i32:
- Opc = X86::MOV32mr;
- RC = X86::GR32RegisterClass;
- break;
- case MVT::i64:
- // Must be in x86-64 mode.
- Opc = X86::MOV64mr;
- RC = X86::GR64RegisterClass;
- break;
+ case MVT::i8: Opc = X86::MOV8mr; break;
+ case MVT::i16: Opc = X86::MOV16mr; break;
+ case MVT::i32: Opc = X86::MOV32mr; break;
+ case MVT::i64: Opc = X86::MOV64mr; break; // Must be in x86-64 mode.
case MVT::f32:
- if (Subtarget->hasSSE1()) {
- Opc = X86::MOVSSmr;
- RC = X86::FR32RegisterClass;
- } else {
- Opc = X86::ST_Fp32m;
- RC = X86::RFP32RegisterClass;
- }
+ Opc = Subtarget->hasSSE1() ? X86::MOVSSmr : X86::ST_Fp32m;
break;
case MVT::f64:
- if (Subtarget->hasSSE2()) {
- Opc = X86::MOVSDmr;
- RC = X86::FR64RegisterClass;
- } else {
- Opc = X86::ST_Fp64m;
- RC = X86::RFP64RegisterClass;
- }
- break;
- case MVT::f80:
- Opc = X86::ST_FP80m;
- RC = X86::RFP80RegisterClass;
+ Opc = Subtarget->hasSSE2() ? X86::MOVSDmr : X86::ST_Fp64m;
break;
}
-
+
addFullAddress(BuildMI(MBB, TII.get(Opc)), AM).addReg(Val);
return true;
}
+bool X86FastISel::X86FastEmitStore(MVT VT, Value *Val,
+ const X86AddressMode &AM) {
+ // Handle 'null' like i32/i64 0.
+ if (isa<ConstantPointerNull>(Val))
+ Val = Constant::getNullValue(TD.getIntPtrType());
+
+ // If this is a store of a simple constant, fold the constant into the store.
+ if (ConstantInt *CI = dyn_cast<ConstantInt>(Val)) {
+ unsigned Opc = 0;
+ switch (VT.getSimpleVT()) {
+ default: break;
+ case MVT::i8: Opc = X86::MOV8mi; break;
+ case MVT::i16: Opc = X86::MOV16mi; break;
+ case MVT::i32: Opc = X86::MOV32mi; break;
+ case MVT::i64:
+ // Must be a 32-bit sign extended value.
+ if ((int)CI->getSExtValue() == CI->getSExtValue())
+ Opc = X86::MOV64mi32;
+ break;
+ }
+
+ if (Opc) {
+ addFullAddress(BuildMI(MBB, TII.get(Opc)), AM).addImm(CI->getSExtValue());
+ return true;
+ }
+ }
+
+ unsigned ValReg = getRegForValue(Val);
+ if (ValReg == 0)
+ return false;
+
+ return X86FastEmitStore(VT, ValReg, AM);
+}
+
/// X86FastEmitExtend - Emit a machine instruction to extend a value Src of
/// type SrcVT to type DstVT using the specified extension opcode Opc (e.g.
/// ISD::SIGN_EXTEND).
// Look past no-op inttoptrs.
if (TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy())
return X86SelectAddress(U->getOperand(0), AM, isCall);
+ break;
case Instruction::PtrToInt:
// Look past no-op ptrtoints.
if (TLI.getValueType(U->getType()) == TLI.getPointerTy())
return X86SelectAddress(U->getOperand(0), AM, isCall);
+ break;
case Instruction::Alloca: {
if (isCall) break;
// Do static allocas.
const AllocaInst *A = cast<AllocaInst>(V);
DenseMap<const AllocaInst*, int>::iterator SI = StaticAllocaMap.find(A);
- if (SI == StaticAllocaMap.end())
- return false;
- AM.BaseType = X86AddressMode::FrameIndexBase;
- AM.Base.FrameIndex = SI->second;
- return true;
+ if (SI != StaticAllocaMap.end()) {
+ AM.BaseType = X86AddressMode::FrameIndexBase;
+ AM.Base.FrameIndex = SI->second;
+ return true;
+ }
+ break;
}
case Instruction::Add: {
if (isCall) break;
// Adds of constants are common and easy enough.
if (ConstantInt *CI = dyn_cast<ConstantInt>(U->getOperand(1))) {
- AM.Disp += CI->getZExtValue();
- return X86SelectAddress(U->getOperand(0), AM, isCall);
+ uint64_t Disp = (int32_t)AM.Disp + (uint64_t)CI->getSExtValue();
+ // They have to fit in the 32-bit signed displacement field though.
+ if (isInt32(Disp)) {
+ AM.Disp = (uint32_t)Disp;
+ return X86SelectAddress(U->getOperand(0), AM, isCall);
+ }
}
break;
}
case Instruction::GetElementPtr: {
if (isCall) break;
// Pattern-match simple GEPs.
- uint64_t Disp = AM.Disp;
+ uint64_t Disp = (int32_t)AM.Disp;
unsigned IndexReg = AM.IndexReg;
unsigned Scale = AM.Scale;
gep_type_iterator GTI = gep_type_begin(U);
- // Look at all but the last index. Constants can be folded,
- // and one dynamic index can be handled, if the scale is supported.
+ // Iterate through the indices, folding what we can. Constants can be
+ // folded, and one dynamic index can be handled, if the scale is supported.
for (User::op_iterator i = U->op_begin() + 1, e = U->op_end();
i != e; ++i, ++GTI) {
Value *Op = *i;
unsigned Idx = cast<ConstantInt>(Op)->getZExtValue();
Disp += SL->getElementOffset(Idx);
} else {
- uint64_t S = TD.getABITypeSize(GTI.getIndexedType());
+ uint64_t S = TD.getTypePaddedSize(GTI.getIndexedType());
if (ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
// Constant-offset addressing.
- Disp += CI->getZExtValue() * S;
+ Disp += CI->getSExtValue() * S;
} else if (IndexReg == 0 &&
+ (!AM.GV ||
+ !getTargetMachine()->symbolicAddressesAreRIPRel()) &&
(S == 1 || S == 2 || S == 4 || S == 8)) {
// Scaled-index addressing.
Scale = S;
- IndexReg = getRegForValue(Op);
+ IndexReg = getRegForGEPIndex(Op);
if (IndexReg == 0)
return false;
} else
goto unsupported_gep;
}
}
+ // Check for displacement overflow.
+ if (!isInt32(Disp))
+ break;
// Ok, the GEP indices were covered by constant-offset and scaled-index
// addressing. Update the address state and move on to examining the base.
AM.IndexReg = IndexReg;
AM.Scale = Scale;
- AM.Disp = Disp;
+ AM.Disp = (uint32_t)Disp;
return X86SelectAddress(U->getOperand(0), AM, isCall);
unsupported_gep:
// Ok, the GEP indices weren't all covered.
// Handle constant address.
if (GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
+ // Can't handle alternate code models yet.
+ if (TM.getCodeModel() != CodeModel::Default &&
+ TM.getCodeModel() != CodeModel::Small)
+ return false;
+
+ // RIP-relative addresses can't have additional register operands.
+ if (getTargetMachine()->symbolicAddressesAreRIPRel() &&
+ (AM.Base.Reg != 0 || AM.IndexReg != 0))
+ return false;
+
+ // Set up the basic address.
+ AM.GV = GV;
+ if (!isCall &&
+ TM.getRelocationModel() == Reloc::PIC_ &&
+ !Subtarget->is64Bit())
+ AM.Base.Reg = getInstrInfo()->getGlobalBaseReg(&MF);
+
+ // Emit an extra load if the ABI requires it.
if (Subtarget->GVRequiresExtraLoad(GV, TM, isCall)) {
// Check to see if we've already materialized this
// value in a register in this block.
if (unsigned Reg = LocalValueMap[V]) {
AM.Base.Reg = Reg;
+ AM.GV = 0;
return true;
}
// Issue load from stub if necessary.
Opc = X86::MOV64rm;
RC = X86::GR64RegisterClass;
}
- AM.Base.Reg = createResultReg(RC);
- X86AddressMode LocalAM;
- LocalAM.GV = GV;
- addFullAddress(BuildMI(MBB, TII.get(Opc), AM.Base.Reg), LocalAM);
+
+ X86AddressMode StubAM;
+ StubAM.Base.Reg = AM.Base.Reg;
+ StubAM.GV = AM.GV;
+ unsigned ResultReg = createResultReg(RC);
+ addFullAddress(BuildMI(MBB, TII.get(Opc), ResultReg), StubAM);
+
+ // Now construct the final address. Note that the Disp, Scale,
+ // and Index values may already be set here.
+ AM.Base.Reg = ResultReg;
+ AM.GV = 0;
+
// Prevent loading GV stub multiple times in same MBB.
LocalValueMap[V] = AM.Base.Reg;
- } else {
- AM.GV = GV;
}
return true;
}
- // If all else fails, just materialize the value in a register.
- AM.Base.Reg = getRegForValue(V);
- return AM.Base.Reg != 0;
+ // If all else fails, try to materialize the value in a register.
+ if (!AM.GV || !getTargetMachine()->symbolicAddressesAreRIPRel()) {
+ if (AM.Base.Reg == 0) {
+ AM.Base.Reg = getRegForValue(V);
+ return AM.Base.Reg != 0;
+ }
+ if (AM.IndexReg == 0) {
+ assert(AM.Scale == 1 && "Scale with no index!");
+ AM.IndexReg = getRegForValue(V);
+ return AM.IndexReg != 0;
+ }
+ }
+
+ return false;
}
/// X86SelectStore - Select and emit code to implement store instructions.
bool X86FastISel::X86SelectStore(Instruction* I) {
MVT VT;
- if (!isTypeLegal(I->getOperand(0)->getType(), TLI, VT))
+ if (!isTypeLegal(I->getOperand(0)->getType(), VT))
return false;
- unsigned Val = getRegForValue(I->getOperand(0));
- if (Val == 0)
- // Unhandled operand. Halt "fast" selection and bail.
- return false;
X86AddressMode AM;
if (!X86SelectAddress(I->getOperand(1), AM, false))
return false;
- return X86FastEmitStore(VT, Val, AM);
+ return X86FastEmitStore(VT, I->getOperand(0), AM);
}
/// X86SelectLoad - Select and emit code to implement load instructions.
///
bool X86FastISel::X86SelectLoad(Instruction *I) {
MVT VT;
- if (!isTypeLegal(I->getType(), TLI, VT))
+ if (!isTypeLegal(I->getType(), VT))
return false;
X86AddressMode AM;
return false;
}
-bool X86FastISel::X86SelectCmp(Instruction *I) {
- CmpInst *CI = cast<CmpInst>(I);
+static unsigned X86ChooseCmpOpcode(MVT VT) {
+ switch (VT.getSimpleVT()) {
+ default: return 0;
+ case MVT::i8: return X86::CMP8rr;
+ case MVT::i16: return X86::CMP16rr;
+ case MVT::i32: return X86::CMP32rr;
+ case MVT::i64: return X86::CMP64rr;
+ case MVT::f32: return X86::UCOMISSrr;
+ case MVT::f64: return X86::UCOMISDrr;
+ }
+}
- MVT VT = TLI.getValueType(I->getOperand(0)->getType());
- if (!TLI.isTypeLegal(VT))
- return false;
+/// X86ChooseCmpImmediateOpcode - If we have a comparison with RHS as the RHS
+/// of the comparison, return an opcode that works for the compare (e.g.
+/// CMP32ri) otherwise return 0.
+static unsigned X86ChooseCmpImmediateOpcode(MVT VT, ConstantInt *RHSC) {
+ switch (VT.getSimpleVT()) {
+ // Otherwise, we can't fold the immediate into this comparison.
+ default: return 0;
+ case MVT::i8: return X86::CMP8ri;
+ case MVT::i16: return X86::CMP16ri;
+ case MVT::i32: return X86::CMP32ri;
+ case MVT::i64:
+ // 64-bit comparisons are only valid if the immediate fits in a 32-bit sext
+ // field.
+ if ((int)RHSC->getSExtValue() == RHSC->getSExtValue())
+ return X86::CMP64ri32;
+ return 0;
+ }
+}
- unsigned Op0Reg = getRegForValue(CI->getOperand(0));
+bool X86FastISel::X86FastEmitCompare(Value *Op0, Value *Op1, MVT VT) {
+ unsigned Op0Reg = getRegForValue(Op0);
if (Op0Reg == 0) return false;
- unsigned Op1Reg = getRegForValue(CI->getOperand(1));
+
+ // Handle 'null' like i32/i64 0.
+ if (isa<ConstantPointerNull>(Op1))
+ Op1 = Constant::getNullValue(TD.getIntPtrType());
+
+ // We have two options: compare with register or immediate. If the RHS of
+ // the compare is an immediate that we can fold into this compare, use
+ // CMPri, otherwise use CMPrr.
+ if (ConstantInt *Op1C = dyn_cast<ConstantInt>(Op1)) {
+ if (unsigned CompareImmOpc = X86ChooseCmpImmediateOpcode(VT, Op1C)) {
+ BuildMI(MBB, TII.get(CompareImmOpc)).addReg(Op0Reg)
+ .addImm(Op1C->getSExtValue());
+ return true;
+ }
+ }
+
+ unsigned CompareOpc = X86ChooseCmpOpcode(VT);
+ if (CompareOpc == 0) return false;
+
+ unsigned Op1Reg = getRegForValue(Op1);
if (Op1Reg == 0) return false;
+ BuildMI(MBB, TII.get(CompareOpc)).addReg(Op0Reg).addReg(Op1Reg);
+
+ return true;
+}
- unsigned Opc;
- switch (VT.getSimpleVT()) {
- case MVT::i8: Opc = X86::CMP8rr; break;
- case MVT::i16: Opc = X86::CMP16rr; break;
- case MVT::i32: Opc = X86::CMP32rr; break;
- case MVT::i64: Opc = X86::CMP64rr; break;
- case MVT::f32: Opc = X86::UCOMISSrr; break;
- case MVT::f64: Opc = X86::UCOMISDrr; break;
- default: return false;
- }
+bool X86FastISel::X86SelectCmp(Instruction *I) {
+ CmpInst *CI = cast<CmpInst>(I);
+
+ MVT VT;
+ if (!isTypeLegal(I->getOperand(0)->getType(), VT))
+ return false;
unsigned ResultReg = createResultReg(&X86::GR8RegClass);
+ unsigned SetCCOpc;
+ bool SwapArgs; // false -> compare Op0, Op1. true -> compare Op1, Op0.
switch (CI->getPredicate()) {
case CmpInst::FCMP_OEQ: {
+ if (!X86FastEmitCompare(CI->getOperand(0), CI->getOperand(1), VT))
+ return false;
+
unsigned EReg = createResultReg(&X86::GR8RegClass);
unsigned NPReg = createResultReg(&X86::GR8RegClass);
- BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
BuildMI(MBB, TII.get(X86::SETEr), EReg);
BuildMI(MBB, TII.get(X86::SETNPr), NPReg);
BuildMI(MBB, TII.get(X86::AND8rr), ResultReg).addReg(NPReg).addReg(EReg);
- break;
+ UpdateValueMap(I, ResultReg);
+ return true;
}
case CmpInst::FCMP_UNE: {
+ if (!X86FastEmitCompare(CI->getOperand(0), CI->getOperand(1), VT))
+ return false;
+
unsigned NEReg = createResultReg(&X86::GR8RegClass);
unsigned PReg = createResultReg(&X86::GR8RegClass);
- BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
BuildMI(MBB, TII.get(X86::SETNEr), NEReg);
BuildMI(MBB, TII.get(X86::SETPr), PReg);
BuildMI(MBB, TII.get(X86::OR8rr), ResultReg).addReg(PReg).addReg(NEReg);
- break;
+ UpdateValueMap(I, ResultReg);
+ return true;
}
- case CmpInst::FCMP_OGT:
- BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
- BuildMI(MBB, TII.get(X86::SETAr), ResultReg);
- break;
- case CmpInst::FCMP_OGE:
- BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
- BuildMI(MBB, TII.get(X86::SETAEr), ResultReg);
- break;
- case CmpInst::FCMP_OLT:
- BuildMI(MBB, TII.get(Opc)).addReg(Op1Reg).addReg(Op0Reg);
- BuildMI(MBB, TII.get(X86::SETAr), ResultReg);
- break;
- case CmpInst::FCMP_OLE:
- BuildMI(MBB, TII.get(Opc)).addReg(Op1Reg).addReg(Op0Reg);
- BuildMI(MBB, TII.get(X86::SETAEr), ResultReg);
- break;
- case CmpInst::FCMP_ONE:
- BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
- BuildMI(MBB, TII.get(X86::SETNEr), ResultReg);
- break;
- case CmpInst::FCMP_ORD:
- BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
- BuildMI(MBB, TII.get(X86::SETNPr), ResultReg);
- break;
- case CmpInst::FCMP_UNO:
- BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
- BuildMI(MBB, TII.get(X86::SETPr), ResultReg);
- break;
- case CmpInst::FCMP_UEQ:
- BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
- BuildMI(MBB, TII.get(X86::SETEr), ResultReg);
- break;
- case CmpInst::FCMP_UGT:
- BuildMI(MBB, TII.get(Opc)).addReg(Op1Reg).addReg(Op0Reg);
- BuildMI(MBB, TII.get(X86::SETBr), ResultReg);
- break;
- case CmpInst::FCMP_UGE:
- BuildMI(MBB, TII.get(Opc)).addReg(Op1Reg).addReg(Op0Reg);
- BuildMI(MBB, TII.get(X86::SETBEr), ResultReg);
- break;
- case CmpInst::FCMP_ULT:
- BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
- BuildMI(MBB, TII.get(X86::SETBr), ResultReg);
- break;
- case CmpInst::FCMP_ULE:
- BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
- BuildMI(MBB, TII.get(X86::SETBEr), ResultReg);
- break;
- case CmpInst::ICMP_EQ:
- BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
- BuildMI(MBB, TII.get(X86::SETEr), ResultReg);
- break;
- case CmpInst::ICMP_NE:
- BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
- BuildMI(MBB, TII.get(X86::SETNEr), ResultReg);
- break;
- case CmpInst::ICMP_UGT:
- BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
- BuildMI(MBB, TII.get(X86::SETAr), ResultReg);
- break;
- case CmpInst::ICMP_UGE:
- BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
- BuildMI(MBB, TII.get(X86::SETAEr), ResultReg);
- break;
- case CmpInst::ICMP_ULT:
- BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
- BuildMI(MBB, TII.get(X86::SETBr), ResultReg);
- break;
- case CmpInst::ICMP_ULE:
- BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
- BuildMI(MBB, TII.get(X86::SETBEr), ResultReg);
- break;
- case CmpInst::ICMP_SGT:
- BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
- BuildMI(MBB, TII.get(X86::SETGr), ResultReg);
- break;
- case CmpInst::ICMP_SGE:
- BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
- BuildMI(MBB, TII.get(X86::SETGEr), ResultReg);
- break;
- case CmpInst::ICMP_SLT:
- BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
- BuildMI(MBB, TII.get(X86::SETLr), ResultReg);
- break;
- case CmpInst::ICMP_SLE:
- BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
- BuildMI(MBB, TII.get(X86::SETLEr), ResultReg);
- break;
+ case CmpInst::FCMP_OGT: SwapArgs = false; SetCCOpc = X86::SETAr; break;
+ case CmpInst::FCMP_OGE: SwapArgs = false; SetCCOpc = X86::SETAEr; break;
+ case CmpInst::FCMP_OLT: SwapArgs = true; SetCCOpc = X86::SETAr; break;
+ case CmpInst::FCMP_OLE: SwapArgs = true; SetCCOpc = X86::SETAEr; break;
+ case CmpInst::FCMP_ONE: SwapArgs = false; SetCCOpc = X86::SETNEr; break;
+ case CmpInst::FCMP_ORD: SwapArgs = false; SetCCOpc = X86::SETNPr; break;
+ case CmpInst::FCMP_UNO: SwapArgs = false; SetCCOpc = X86::SETPr; break;
+ case CmpInst::FCMP_UEQ: SwapArgs = false; SetCCOpc = X86::SETEr; break;
+ case CmpInst::FCMP_UGT: SwapArgs = true; SetCCOpc = X86::SETBr; break;
+ case CmpInst::FCMP_UGE: SwapArgs = true; SetCCOpc = X86::SETBEr; break;
+ case CmpInst::FCMP_ULT: SwapArgs = false; SetCCOpc = X86::SETBr; break;
+ case CmpInst::FCMP_ULE: SwapArgs = false; SetCCOpc = X86::SETBEr; break;
+
+ case CmpInst::ICMP_EQ: SwapArgs = false; SetCCOpc = X86::SETEr; break;
+ case CmpInst::ICMP_NE: SwapArgs = false; SetCCOpc = X86::SETNEr; break;
+ case CmpInst::ICMP_UGT: SwapArgs = false; SetCCOpc = X86::SETAr; break;
+ case CmpInst::ICMP_UGE: SwapArgs = false; SetCCOpc = X86::SETAEr; break;
+ case CmpInst::ICMP_ULT: SwapArgs = false; SetCCOpc = X86::SETBr; break;
+ case CmpInst::ICMP_ULE: SwapArgs = false; SetCCOpc = X86::SETBEr; break;
+ case CmpInst::ICMP_SGT: SwapArgs = false; SetCCOpc = X86::SETGr; break;
+ case CmpInst::ICMP_SGE: SwapArgs = false; SetCCOpc = X86::SETGEr; break;
+ case CmpInst::ICMP_SLT: SwapArgs = false; SetCCOpc = X86::SETLr; break;
+ case CmpInst::ICMP_SLE: SwapArgs = false; SetCCOpc = X86::SETLEr; break;
default:
return false;
}
+ Value *Op0 = CI->getOperand(0), *Op1 = CI->getOperand(1);
+ if (SwapArgs)
+ std::swap(Op0, Op1);
+
+ // Emit a compare of Op0/Op1.
+ if (!X86FastEmitCompare(Op0, Op1, VT))
+ return false;
+
+ BuildMI(MBB, TII.get(SetCCOpc), ResultReg);
UpdateValueMap(I, ResultReg);
return true;
}
return false;
}
+
bool X86FastISel::X86SelectBranch(Instruction *I) {
- BranchInst *BI = cast<BranchInst>(I);
// Unconditional branches are selected by tablegen-generated code.
- unsigned OpReg = getRegForValue(BI->getCondition());
- if (OpReg == 0) return false;
+ // Handle a conditional branch.
+ BranchInst *BI = cast<BranchInst>(I);
MachineBasicBlock *TrueMBB = MBBMap[BI->getSuccessor(0)];
MachineBasicBlock *FalseMBB = MBBMap[BI->getSuccessor(1)];
+ // Fold the common case of a conditional branch with a comparison.
+ if (CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
+ if (CI->hasOneUse()) {
+ MVT VT = TLI.getValueType(CI->getOperand(0)->getType());
+
+ // Try to take advantage of fallthrough opportunities.
+ CmpInst::Predicate Predicate = CI->getPredicate();
+ if (MBB->isLayoutSuccessor(TrueMBB)) {
+ std::swap(TrueMBB, FalseMBB);
+ Predicate = CmpInst::getInversePredicate(Predicate);
+ }
+
+ bool SwapArgs; // false -> compare Op0, Op1. true -> compare Op1, Op0.
+ unsigned BranchOpc; // Opcode to jump on, e.g. "X86::JA"
+
+ switch (Predicate) {
+ case CmpInst::FCMP_OEQ:
+ std::swap(TrueMBB, FalseMBB);
+ Predicate = CmpInst::FCMP_UNE;
+ // FALL THROUGH
+ case CmpInst::FCMP_UNE: SwapArgs = false; BranchOpc = X86::JNE; break;
+ case CmpInst::FCMP_OGT: SwapArgs = false; BranchOpc = X86::JA; break;
+ case CmpInst::FCMP_OGE: SwapArgs = false; BranchOpc = X86::JAE; break;
+ case CmpInst::FCMP_OLT: SwapArgs = true; BranchOpc = X86::JA; break;
+ case CmpInst::FCMP_OLE: SwapArgs = true; BranchOpc = X86::JAE; break;
+ case CmpInst::FCMP_ONE: SwapArgs = false; BranchOpc = X86::JNE; break;
+ case CmpInst::FCMP_ORD: SwapArgs = false; BranchOpc = X86::JNP; break;
+ case CmpInst::FCMP_UNO: SwapArgs = false; BranchOpc = X86::JP; break;
+ case CmpInst::FCMP_UEQ: SwapArgs = false; BranchOpc = X86::JE; break;
+ case CmpInst::FCMP_UGT: SwapArgs = true; BranchOpc = X86::JB; break;
+ case CmpInst::FCMP_UGE: SwapArgs = true; BranchOpc = X86::JBE; break;
+ case CmpInst::FCMP_ULT: SwapArgs = false; BranchOpc = X86::JB; break;
+ case CmpInst::FCMP_ULE: SwapArgs = false; BranchOpc = X86::JBE; break;
+
+ case CmpInst::ICMP_EQ: SwapArgs = false; BranchOpc = X86::JE; break;
+ case CmpInst::ICMP_NE: SwapArgs = false; BranchOpc = X86::JNE; break;
+ case CmpInst::ICMP_UGT: SwapArgs = false; BranchOpc = X86::JA; break;
+ case CmpInst::ICMP_UGE: SwapArgs = false; BranchOpc = X86::JAE; break;
+ case CmpInst::ICMP_ULT: SwapArgs = false; BranchOpc = X86::JB; break;
+ case CmpInst::ICMP_ULE: SwapArgs = false; BranchOpc = X86::JBE; break;
+ case CmpInst::ICMP_SGT: SwapArgs = false; BranchOpc = X86::JG; break;
+ case CmpInst::ICMP_SGE: SwapArgs = false; BranchOpc = X86::JGE; break;
+ case CmpInst::ICMP_SLT: SwapArgs = false; BranchOpc = X86::JL; break;
+ case CmpInst::ICMP_SLE: SwapArgs = false; BranchOpc = X86::JLE; break;
+ default:
+ return false;
+ }
+
+ Value *Op0 = CI->getOperand(0), *Op1 = CI->getOperand(1);
+ if (SwapArgs)
+ std::swap(Op0, Op1);
+
+ // Emit a compare of the LHS and RHS, setting the flags.
+ if (!X86FastEmitCompare(Op0, Op1, VT))
+ return false;
+
+ BuildMI(MBB, TII.get(BranchOpc)).addMBB(TrueMBB);
+
+ if (Predicate == CmpInst::FCMP_UNE) {
+ // X86 requires a second branch to handle UNE (and OEQ,
+ // which is mapped to UNE above).
+ BuildMI(MBB, TII.get(X86::JP)).addMBB(TrueMBB);
+ }
+
+ FastEmitBranch(FalseMBB);
+ MBB->addSuccessor(TrueMBB);
+ return true;
+ }
+ } else if (ExtractValueInst *EI =
+ dyn_cast<ExtractValueInst>(BI->getCondition())) {
+ // Check to see if the branch instruction is from an "arithmetic with
+ // overflow" intrinsic. The main way these intrinsics are used is:
+ //
+ // %t = call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 %v1, i32 %v2)
+ // %sum = extractvalue { i32, i1 } %t, 0
+ // %obit = extractvalue { i32, i1 } %t, 1
+ // br i1 %obit, label %overflow, label %normal
+ //
+ // The %sum and %obit are converted in an ADD and a SETO/SETB before
+ // reaching the branch. Therefore, we search backwards through the MBB
+ // looking for the SETO/SETB instruction. If an instruction modifies the
+ // EFLAGS register before we reach the SETO/SETB instruction, then we can't
+ // convert the branch into a JO/JB instruction.
+
+ Value *Agg = EI->getAggregateOperand();
+
+ if (CallInst *CI = dyn_cast<CallInst>(Agg)) {
+ Function *F = CI->getCalledFunction();
+
+ if (F && F->isDeclaration()) {
+ switch (F->getIntrinsicID()) {
+ default: break;
+ case Intrinsic::sadd_with_overflow:
+ case Intrinsic::uadd_with_overflow: {
+ const MachineInstr *SetMI = 0;
+ unsigned Reg = lookUpRegForValue(EI);
+
+ for (MachineBasicBlock::const_reverse_iterator
+ RI = MBB->rbegin(), RE = MBB->rend(); RI != RE; ++RI) {
+ const MachineInstr &MI = *RI;
+
+ if (MI.modifiesRegister(Reg)) {
+ unsigned Src, Dst, SrcSR, DstSR;
+
+ if (getInstrInfo()->isMoveInstr(MI, Src, Dst, SrcSR, DstSR)) {
+ Reg = Src;
+ continue;
+ }
+
+ SetMI = &MI;
+ break;
+ }
+
+ const TargetInstrDesc &TID = MI.getDesc();
+ const unsigned *ImpDefs = TID.getImplicitDefs();
+
+ if (TID.hasUnmodeledSideEffects()) break;
+
+ bool ModifiesEFlags = false;
+
+ if (ImpDefs) {
+ for (unsigned u = 0; ImpDefs[u]; ++u)
+ if (ImpDefs[u] == X86::EFLAGS) {
+ ModifiesEFlags = true;
+ break;
+ }
+ }
+
+ if (ModifiesEFlags) break;
+ }
+
+ if (SetMI) {
+ unsigned OpCode = SetMI->getOpcode();
+
+ if (OpCode == X86::SETOr || OpCode == X86::SETBr) {
+ BuildMI(MBB, TII.get((OpCode == X86::SETOr) ?
+ X86::JO : X86::JB)).addMBB(TrueMBB);
+ FastEmitBranch(FalseMBB);
+ MBB->addSuccessor(TrueMBB);
+ return true;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Otherwise do a clumsy setcc and re-test it.
+ unsigned OpReg = getRegForValue(BI->getCondition());
+ if (OpReg == 0) return false;
+
BuildMI(MBB, TII.get(X86::TEST8rr)).addReg(OpReg).addReg(OpReg);
BuildMI(MBB, TII.get(X86::JNE)).addMBB(TrueMBB);
- BuildMI(MBB, TII.get(X86::JMP)).addMBB(FalseMBB);
-
+ FastEmitBranch(FalseMBB);
MBB->addSuccessor(TrueMBB);
- MBB->addSuccessor(FalseMBB);
-
return true;
}
return false;
}
- MVT VT = MVT::getMVT(I->getType(), /*HandleUnknown=*/true);
- if (VT == MVT::Other || !TLI.isTypeLegal(VT))
+ MVT VT = TLI.getValueType(I->getType(), /*HandleUnknown=*/true);
+ if (VT == MVT::Other || !isTypeLegal(I->getType(), VT))
return false;
unsigned Op0Reg = getRegForValue(I->getOperand(0));
if (ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1))) {
unsigned ResultReg = createResultReg(RC);
BuildMI(MBB, TII.get(OpImm),
- ResultReg).addReg(Op0Reg).addImm(CI->getZExtValue());
+ ResultReg).addReg(Op0Reg).addImm(CI->getZExtValue() & 0xff);
UpdateValueMap(I, ResultReg);
return true;
}
unsigned Op1Reg = getRegForValue(I->getOperand(1));
if (Op1Reg == 0) return false;
TII.copyRegToReg(*MBB, MBB->end(), CReg, Op1Reg, RC, RC);
+
+ // The shift instruction uses X86::CL. If we defined a super-register
+ // of X86::CL, emit an EXTRACT_SUBREG to precisely describe what
+ // we're doing here.
+ if (CReg != X86::CL)
+ BuildMI(MBB, TII.get(TargetInstrInfo::EXTRACT_SUBREG), X86::CL)
+ .addReg(CReg).addImm(X86::SUBREG_8BIT);
+
unsigned ResultReg = createResultReg(RC);
BuildMI(MBB, TII.get(OpReg), ResultReg).addReg(Op0Reg);
UpdateValueMap(I, ResultReg);
}
bool X86FastISel::X86SelectSelect(Instruction *I) {
- const Type *Ty = I->getType();
- if (isa<PointerType>(Ty))
- Ty = TD.getIntPtrType();
-
+ MVT VT = TLI.getValueType(I->getType(), /*HandleUnknown=*/true);
+ if (VT == MVT::Other || !isTypeLegal(I->getType(), VT))
+ return false;
+
unsigned Opc = 0;
const TargetRegisterClass *RC = NULL;
- if (Ty == Type::Int16Ty) {
+ if (VT.getSimpleVT() == MVT::i16) {
Opc = X86::CMOVE16rr;
RC = &X86::GR16RegClass;
- } else if (Ty == Type::Int32Ty) {
+ } else if (VT.getSimpleVT() == MVT::i32) {
Opc = X86::CMOVE32rr;
RC = &X86::GR32RegClass;
- } else if (Ty == Type::Int64Ty) {
+ } else if (VT.getSimpleVT() == MVT::i64) {
Opc = X86::CMOVE64rr;
RC = &X86::GR64RegClass;
} else {
return false;
}
- MVT VT = MVT::getMVT(Ty, /*HandleUnknown=*/true);
- if (VT == MVT::Other || !TLI.isTypeLegal(VT))
- return false;
-
unsigned Op0Reg = getRegForValue(I->getOperand(0));
if (Op0Reg == 0) return false;
unsigned Op1Reg = getRegForValue(I->getOperand(1));
}
bool X86FastISel::X86SelectFPExt(Instruction *I) {
- if (Subtarget->hasSSE2()) {
- if (I->getType() == Type::DoubleTy) {
- Value *V = I->getOperand(0);
- if (V->getType() == Type::FloatTy) {
- unsigned OpReg = getRegForValue(V);
- if (OpReg == 0) return false;
- unsigned ResultReg = createResultReg(X86::FR64RegisterClass);
- BuildMI(MBB, TII.get(X86::CVTSS2SDrr), ResultReg).addReg(OpReg);
- UpdateValueMap(I, ResultReg);
- return true;
- }
+ // fpext from float to double.
+ if (Subtarget->hasSSE2() && I->getType() == Type::DoubleTy) {
+ Value *V = I->getOperand(0);
+ if (V->getType() == Type::FloatTy) {
+ unsigned OpReg = getRegForValue(V);
+ if (OpReg == 0) return false;
+ unsigned ResultReg = createResultReg(X86::FR64RegisterClass);
+ BuildMI(MBB, TII.get(X86::CVTSS2SDrr), ResultReg).addReg(OpReg);
+ UpdateValueMap(I, ResultReg);
+ return true;
}
}
BuildMI(MBB, TII.get(CopyOpc), CopyReg).addReg(InputReg);
// Then issue an extract_subreg.
- unsigned ResultReg = FastEmitInst_extractsubreg(CopyReg,1); // x86_subreg_8bit
+ unsigned ResultReg = FastEmitInst_extractsubreg(DstVT.getSimpleVT(),
+ CopyReg, X86::SUBREG_8BIT);
if (!ResultReg)
return false;
return true;
}
+bool X86FastISel::X86SelectExtractValue(Instruction *I) {
+ ExtractValueInst *EI = cast<ExtractValueInst>(I);
+ Value *Agg = EI->getAggregateOperand();
+
+ if (CallInst *CI = dyn_cast<CallInst>(Agg)) {
+ Function *F = CI->getCalledFunction();
+
+ if (F && F->isDeclaration()) {
+ switch (F->getIntrinsicID()) {
+ default: break;
+ case Intrinsic::sadd_with_overflow:
+ case Intrinsic::uadd_with_overflow:
+ // Cheat a little. We know that the registers for "add" and "seto" are
+ // allocated sequentially. However, we only keep track of the register
+ // for "add" in the value map. Use extractvalue's index to get the
+ // correct register for "seto".
+ UpdateValueMap(I, lookUpRegForValue(Agg) + *EI->idx_begin());
+ return true;
+ }
+ }
+ }
+
+ return false;
+}
+
+bool X86FastISel::X86VisitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
+ // FIXME: Handle more intrinsics.
+ switch (Intrinsic) {
+ default: return false;
+ case Intrinsic::sadd_with_overflow:
+ case Intrinsic::uadd_with_overflow: {
+ // Replace "add with overflow" intrinsics with an "add" instruction followed
+ // by a seto/setc instruction. Later on, when the "extractvalue"
+ // instructions are encountered, we use the fact that two registers were
+ // created sequentially to get the correct registers for the "sum" and the
+ // "overflow bit".
+ MVT VT;
+ const Function *Callee = I.getCalledFunction();
+ const Type *RetTy =
+ cast<StructType>(Callee->getReturnType())->getTypeAtIndex(unsigned(0));
+
+ if (!isTypeLegal(RetTy, VT))
+ return false;
+
+ Value *Op1 = I.getOperand(1);
+ Value *Op2 = I.getOperand(2);
+ unsigned Reg1 = getRegForValue(Op1);
+ unsigned Reg2 = getRegForValue(Op2);
+
+ if (Reg1 == 0 || Reg2 == 0)
+ // FIXME: Handle values *not* in registers.
+ return false;
+
+ unsigned OpC = 0;
+
+ if (VT == MVT::i32)
+ OpC = X86::ADD32rr;
+ else if (VT == MVT::i64)
+ OpC = X86::ADD64rr;
+ else
+ return false;
+
+ unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
+ BuildMI(MBB, TII.get(OpC), ResultReg).addReg(Reg1).addReg(Reg2);
+ UpdateValueMap(&I, ResultReg);
+
+ ResultReg = createResultReg(TLI.getRegClassFor(MVT::i8));
+ BuildMI(MBB, TII.get((Intrinsic == Intrinsic::sadd_with_overflow) ?
+ X86::SETOr : X86::SETBr), ResultReg);
+ return true;
+ }
+ }
+}
+
bool X86FastISel::X86SelectCall(Instruction *I) {
CallInst *CI = cast<CallInst>(I);
Value *Callee = I->getOperand(0);
if (isa<InlineAsm>(Callee))
return false;
- // FIXME: Handle some intrinsics.
- if (Function *F = CI->getCalledFunction()) {
- if (F->isDeclaration() &&F->getIntrinsicID())
- return false;
- }
+ // Handle intrinsic calls.
+ if (Function *F = CI->getCalledFunction())
+ if (F->isDeclaration())
+ if (unsigned IID = F->getIntrinsicID())
+ return X86VisitIntrinsicCall(*CI, IID);
// Handle only C and fastcc calling conventions for now.
CallSite CS(CI);
MVT RetVT;
if (RetTy == Type::VoidTy)
RetVT = MVT::isVoid;
- else if (!isTypeLegal(RetTy, TLI, RetVT, true))
+ else if (!isTypeLegal(RetTy, RetVT, true))
return false;
// Materialize callee address in a register. FIXME: GV address can be
}
// Deal with call operands first.
- SmallVector<unsigned, 4> Args;
- SmallVector<MVT, 4> ArgVTs;
- SmallVector<ISD::ArgFlagsTy, 4> ArgFlags;
+ SmallVector<Value*, 8> ArgVals;
+ SmallVector<unsigned, 8> Args;
+ SmallVector<MVT, 8> ArgVTs;
+ SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
Args.reserve(CS.arg_size());
+ ArgVals.reserve(CS.arg_size());
ArgVTs.reserve(CS.arg_size());
ArgFlags.reserve(CS.arg_size());
for (CallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
return false;
ISD::ArgFlagsTy Flags;
unsigned AttrInd = i - CS.arg_begin() + 1;
- if (CS.paramHasAttr(AttrInd, ParamAttr::SExt))
+ if (CS.paramHasAttr(AttrInd, Attribute::SExt))
Flags.setSExt();
- if (CS.paramHasAttr(AttrInd, ParamAttr::ZExt))
+ if (CS.paramHasAttr(AttrInd, Attribute::ZExt))
Flags.setZExt();
// FIXME: Only handle *easy* calls for now.
- if (CS.paramHasAttr(AttrInd, ParamAttr::InReg) ||
- CS.paramHasAttr(AttrInd, ParamAttr::StructRet) ||
- CS.paramHasAttr(AttrInd, ParamAttr::Nest) ||
- CS.paramHasAttr(AttrInd, ParamAttr::ByVal))
+ if (CS.paramHasAttr(AttrInd, Attribute::InReg) ||
+ CS.paramHasAttr(AttrInd, Attribute::StructRet) ||
+ CS.paramHasAttr(AttrInd, Attribute::Nest) ||
+ CS.paramHasAttr(AttrInd, Attribute::ByVal))
return false;
const Type *ArgTy = (*i)->getType();
MVT ArgVT;
- if (!isTypeLegal(ArgTy, TLI, ArgVT))
+ if (!isTypeLegal(ArgTy, ArgVT))
return false;
unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy);
Flags.setOrigAlign(OriginalAlignment);
Args.push_back(Arg);
+ ArgVals.push_back(*i);
ArgVTs.push_back(ArgVT);
ArgFlags.push_back(Flags);
}
unsigned NumBytes = CCInfo.getNextStackOffset();
// Issue CALLSEQ_START
- BuildMI(MBB, TII.get(X86::ADJCALLSTACKDOWN)).addImm(NumBytes);
+ unsigned AdjStackDown = TM.getRegisterInfo()->getCallFrameSetupOpcode();
+ BuildMI(MBB, TII.get(AdjStackDown)).addImm(NumBytes);
- // Process argumenet: walk the register/memloc assignments, inserting
+ // Process argument: walk the register/memloc assignments, inserting
// copies / loads.
SmallVector<unsigned, 4> RegArgs;
for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
case CCValAssign::SExt: {
bool Emitted = X86FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(),
Arg, ArgVT, Arg);
- assert(Emitted && "Failed to emit a sext!");
+ assert(Emitted && "Failed to emit a sext!"); Emitted=Emitted;
+ Emitted = true;
ArgVT = VA.getLocVT();
break;
}
case CCValAssign::ZExt: {
bool Emitted = X86FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(),
Arg, ArgVT, Arg);
- assert(Emitted && "Failed to emit a zext!");
+ assert(Emitted && "Failed to emit a zext!"); Emitted=Emitted;
+ Emitted = true;
ArgVT = VA.getLocVT();
break;
}
Arg, ArgVT, Arg);
if (!Emitted)
Emitted = X86FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(),
- Arg, ArgVT, Arg);
+ Arg, ArgVT, Arg);
if (!Emitted)
Emitted = X86FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(),
Arg, ArgVT, Arg);
- assert(Emitted && "Failed to emit a aext!");
+ assert(Emitted && "Failed to emit a aext!"); Emitted=Emitted;
ArgVT = VA.getLocVT();
break;
}
TargetRegisterClass* RC = TLI.getRegClassFor(ArgVT);
bool Emitted = TII.copyRegToReg(*MBB, MBB->end(), VA.getLocReg(),
Arg, RC, RC);
- assert(Emitted && "Failed to emit a copy instruction!");
+ assert(Emitted && "Failed to emit a copy instruction!"); Emitted=Emitted;
+ Emitted = true;
RegArgs.push_back(VA.getLocReg());
} else {
unsigned LocMemOffset = VA.getLocMemOffset();
X86AddressMode AM;
AM.Base.Reg = StackPtr;
AM.Disp = LocMemOffset;
- X86FastEmitStore(ArgVT, Arg, AM);
+ Value *ArgVal = ArgVals[VA.getValNo()];
+
+ // If this is a really simple value, emit this with the Value* version of
+ // X86FastEmitStore. If it isn't simple, we don't want to do this, as it
+ // can cause us to reevaluate the argument.
+ if (isa<ConstantInt>(ArgVal) || isa<ConstantPointerNull>(ArgVal))
+ X86FastEmitStore(ArgVT, ArgVal, AM);
+ else
+ X86FastEmitStore(ArgVT, Arg, AM);
}
}
+ // ELF / PIC requires GOT in the EBX register before function calls via PLT
+ // GOT pointer.
+ if (!Subtarget->is64Bit() &&
+ TM.getRelocationModel() == Reloc::PIC_ &&
+ Subtarget->isPICStyleGOT()) {
+ TargetRegisterClass *RC = X86::GR32RegisterClass;
+ unsigned Base = getInstrInfo()->getGlobalBaseReg(&MF);
+ bool Emitted = TII.copyRegToReg(*MBB, MBB->end(), X86::EBX, Base, RC, RC);
+ assert(Emitted && "Failed to emit a copy instruction!"); Emitted=Emitted;
+ Emitted = true;
+ }
+
// Issue the call.
unsigned CallOpc = CalleeOp
? (Subtarget->is64Bit() ? X86::CALL64r : X86::CALL32r)
MachineInstrBuilder MIB = CalleeOp
? BuildMI(MBB, TII.get(CallOpc)).addReg(CalleeOp)
: BuildMI(MBB, TII.get(CallOpc)).addGlobalAddress(GV);
+
+ // Add an implicit use GOT pointer in EBX.
+ if (!Subtarget->is64Bit() &&
+ TM.getRelocationModel() == Reloc::PIC_ &&
+ Subtarget->isPICStyleGOT())
+ MIB.addReg(X86::EBX);
+
// Add implicit physical register uses to the call.
- while (!RegArgs.empty()) {
- MIB.addReg(RegArgs.back());
- RegArgs.pop_back();
- }
+ for (unsigned i = 0, e = RegArgs.size(); i != e; ++i)
+ MIB.addReg(RegArgs[i]);
// Issue CALLSEQ_END
- BuildMI(MBB, TII.get(X86::ADJCALLSTACKUP)).addImm(NumBytes).addImm(0);
+ unsigned AdjStackUp = TM.getRegisterInfo()->getCallFrameDestroyOpcode();
+ BuildMI(MBB, TII.get(AdjStackUp)).addImm(NumBytes).addImm(0);
// Now handle call return value (if any).
if (RetVT.getSimpleVT() != MVT::isVoid) {
unsigned ResultReg = createResultReg(DstRC);
bool Emitted = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
RVLocs[0].getLocReg(), DstRC, SrcRC);
- assert(Emitted && "Failed to emit a copy instruction!");
+ assert(Emitted && "Failed to emit a copy instruction!"); Emitted=Emitted;
+ Emitted = true;
if (CopyVT != RVLocs[0].getValVT()) {
// Round the F80 the right size, which also moves to the appropriate xmm
// register. This is accomplished by storing the F80 value in memory and
return X86SelectFPExt(I);
case Instruction::FPTrunc:
return X86SelectFPTrunc(I);
+ case Instruction::ExtractValue:
+ return X86SelectExtractValue(I);
}
return false;
}
unsigned X86FastISel::TargetMaterializeConstant(Constant *C) {
- // Can't handle PIC-mode yet.
- if (TM.getRelocationModel() == Reloc::PIC_)
- return 0;
-
MVT VT;
- if (!isTypeLegal(C->getType(), TLI, VT))
+ if (!isTypeLegal(C->getType(), VT))
return false;
// Get opcode and regclass of the output for the given load instruction.
}
break;
case MVT::f80:
- Opc = X86::LD_Fp80m;
- RC = X86::RFP80RegisterClass;
- break;
+ // No f80 support yet.
+ return false;
}
// Materialize addresses with LEA instructions.
unsigned Align = TD.getPreferredTypeAlignmentShift(C->getType());
if (Align == 0) {
// Alignment of vector types. FIXME!
- Align = TD.getABITypeSize(C->getType());
+ Align = TD.getTypePaddedSize(C->getType());
Align = Log2_64(Align);
}
+ // x86-32 PIC requires a PIC base register for constant pools.
+ unsigned PICBase = 0;
+ if (TM.getRelocationModel() == Reloc::PIC_ &&
+ !Subtarget->is64Bit())
+ PICBase = getInstrInfo()->getGlobalBaseReg(&MF);
+
+ // Create the load from the constant pool.
unsigned MCPOffset = MCP.getConstantPoolIndex(C, Align);
unsigned ResultReg = createResultReg(RC);
- addConstantPoolReference(BuildMI(MBB, TII.get(Opc), ResultReg), MCPOffset);
+ addConstantPoolReference(BuildMI(MBB, TII.get(Opc), ResultReg), MCPOffset,
+ PICBase);
+
return ResultReg;
}
unsigned X86FastISel::TargetMaterializeAlloca(AllocaInst *C) {
+ // Fail on dynamic allocas. At this point, getRegForValue has already
+ // checked its CSE maps, so if we're here trying to handle a dynamic
+ // alloca, we're not going to succeed. X86SelectAddress has a
+ // check for dynamic allocas, because it's called directly from
+ // various places, but TargetMaterializeAlloca also needs a check
+ // in order to avoid recursion between getRegForValue,
+ // X86SelectAddrss, and TargetMaterializeAlloca.
+ if (!StaticAllocaMap.count(C))
+ return 0;
+
X86AddressMode AM;
if (!X86SelectAddress(C, AM, false))
return 0;
namespace llvm {
llvm::FastISel *X86::createFastISel(MachineFunction &mf,
+ MachineModuleInfo *mmi,
+ DwarfWriter *dw,
DenseMap<const Value *, unsigned> &vm,
DenseMap<const BasicBlock *, MachineBasicBlock *> &bm,
- DenseMap<const AllocaInst *, int> &am) {
- return new X86FastISel(mf, vm, bm, am);
+ DenseMap<const AllocaInst *, int> &am
+#ifndef NDEBUG
+ , SmallSet<Instruction*, 8> &cil
+#endif
+ ) {
+ return new X86FastISel(mf, mmi, dw, vm, bm, am
+#ifndef NDEBUG
+ , cil
+#endif
+ );
}
}
projects / oota-llvm.git / blobdiff