#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/Support/CallSite.h"
+#include "llvm/Support/GetElementPtrTypeIterator.h"
using namespace llvm;
class X86FastISel : public FastISel {
- /// MFI - Keep track of objects allocated on the stack.
- ///
- MachineFrameInfo *MFI;
-
/// Subtarget - Keep a pointer to the X86Subtarget around so that we can
/// make the right decision when generating code for different targets.
const X86Subtarget *Subtarget;
public:
explicit X86FastISel(MachineFunction &mf,
+ MachineModuleInfo *mmi,
DenseMap<const Value *, unsigned> &vm,
- DenseMap<const BasicBlock *, MachineBasicBlock *> &bm)
- : FastISel(mf, vm, bm), MFI(MF.getFrameInfo()) {
+ DenseMap<const BasicBlock *, MachineBasicBlock *> &bm,
+ DenseMap<const AllocaInst *, int> &am)
+ : FastISel(mf, mmi, vm, bm, am) {
Subtarget = &TM.getSubtarget<X86Subtarget>();
StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
X86ScalarSSEf64 = Subtarget->hasSSE2();
#include "X86GenFastISel.inc"
private:
- bool X86FastEmitLoad(MVT VT, unsigned Op0, Value *V, unsigned &RR);
+ bool X86FastEmitLoad(MVT VT, const X86AddressMode &AM, unsigned &RR);
bool X86FastEmitStore(MVT VT, unsigned Val,
- unsigned Ptr, unsigned Offset, Value *V);
+ const X86AddressMode &AM);
bool X86FastEmitExtend(ISD::NodeType Opc, MVT DstVT, unsigned Src, MVT SrcVT,
unsigned &ResultReg);
- bool X86SelectConstAddr(Value *V, unsigned &Op0, bool isCall = false);
+ bool X86SelectAddress(Value *V, X86AddressMode &AM, bool isCall);
bool X86SelectLoad(Instruction *I);
bool X86SelectSelect(Instruction *I);
bool X86SelectTrunc(Instruction *I);
+
+ unsigned X86ChooseCmpOpcode(MVT VT);
+
+ bool X86SelectFPExt(Instruction *I);
+ bool X86SelectFPTrunc(Instruction *I);
bool X86SelectCall(Instruction *I);
CCAssignFn *CCAssignFnForCall(unsigned CC, bool isTailCall = false);
- unsigned TargetMaterializeConstant(Constant *C, MachineConstantPool* MCP);
+ const X86InstrInfo *getInstrInfo() const {
+ return getTargetMachine()->getInstrInfo();
+ }
+ const X86TargetMachine *getTargetMachine() const {
+ return static_cast<const X86TargetMachine *>(&TM);
+ }
+
+ unsigned TargetMaterializeConstant(Constant *C);
+
+ unsigned TargetMaterializeAlloca(AllocaInst *C);
/// isScalarFPTypeInSSEReg - Return true if the specified scalar FP type is
/// computed in an SSE register, not on the X87 floating point stack.
(VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1
}
+ bool isTypeLegal(const Type *Ty, const TargetLowering &TLI, MVT &VT,
+ bool AllowI1 = false);
};
-static bool isTypeLegal(const Type *Ty, const TargetLowering &TLI, MVT &VT,
- bool AllowI1 = false) {
+bool X86FastISel::isTypeLegal(const Type *Ty, const TargetLowering &TLI,
+ MVT &VT, bool AllowI1) {
VT = MVT::getMVT(Ty, /*HandleUnknown=*/true);
if (VT == MVT::Other || !VT.isSimple())
// Unhandled type. Halt "fast" selection and bail.
if (VT == MVT::iPTR)
// Use pointer type.
VT = TLI.getPointerTy();
+ // For now, require SSE/SSE2 for performing floating-point operations,
+ // since x87 requires additional work.
+ if (VT == MVT::f64 && !X86ScalarSSEf64)
+ return false;
+ if (VT == MVT::f32 && !X86ScalarSSEf32)
+ return false;
+ // Similarly, no f80 support yet.
+ if (VT == MVT::f80)
+ return false;
// We only handle legal types. For example, on x86-32 the instruction
// selector contains all of the 64-bit instructions from x86-64,
// under the assumption that i64 won't be used if the target doesn't
if (CC == CallingConv::X86_FastCall)
return CC_X86_32_FastCall;
- else if (CC == CallingConv::Fast && isTaillCall)
- return CC_X86_32_TailCall;
else if (CC == CallingConv::Fast)
return CC_X86_32_FastCC;
else
/// X86FastEmitLoad - Emit a machine instruction to load a value of type VT.
/// The address is either pre-computed, i.e. Ptr, or a GlobalAddress, i.e. GV.
/// Return true and the result register by reference if it is possible.
-bool X86FastISel::X86FastEmitLoad(MVT VT, unsigned Ptr, Value *GV,
+bool X86FastISel::X86FastEmitLoad(MVT VT, const X86AddressMode &AM,
unsigned &ResultReg) {
// Get opcode and regclass of the output for the given load instruction.
unsigned Opc = 0;
}
break;
case MVT::f80:
- Opc = X86::LD_Fp80m;
- RC = X86::RFP80RegisterClass;
- break;
+ // No f80 support yet.
+ return false;
}
ResultReg = createResultReg(RC);
- X86AddressMode AM;
- if (Ptr)
- // Address is in register.
- AM.Base.Reg = Ptr;
- else
- AM.GV = cast<GlobalValue>(GV);
addFullAddress(BuildMI(MBB, TII.get(Opc), ResultReg), AM);
return true;
}
/// i.e. V. Return true if it is possible.
bool
X86FastISel::X86FastEmitStore(MVT VT, unsigned Val,
- unsigned Ptr, unsigned Offset, Value *V) {
+ const X86AddressMode &AM) {
// Get opcode and regclass of the output for the given store instruction.
unsigned Opc = 0;
const TargetRegisterClass *RC = NULL;
}
break;
case MVT::f80:
- Opc = X86::ST_FP80m;
- RC = X86::RFP80RegisterClass;
- break;
+ // No f80 support yet.
+ return false;
}
- X86AddressMode AM;
- if (Ptr) {
- // Address is in register.
- AM.Base.Reg = Ptr;
- AM.Disp = Offset;
- } else
- AM.GV = cast<GlobalValue>(V);
addFullAddress(BuildMI(MBB, TII.get(Opc)), AM).addReg(Val);
return true;
}
bool X86FastISel::X86FastEmitExtend(ISD::NodeType Opc, MVT DstVT,
unsigned Src, MVT SrcVT,
unsigned &ResultReg) {
- ResultReg = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Opc, Src);
- return ResultReg != 0;
+ unsigned RR = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Opc, Src);
+
+ if (RR != 0) {
+ ResultReg = RR;
+ return true;
+ } else
+ return false;
}
-/// X86SelectConstAddr - Select and emit code to materialize constant address.
-///
-bool X86FastISel::X86SelectConstAddr(Value *V, unsigned &Op0, bool isCall) {
- // FIXME: Only GlobalAddress for now.
- GlobalValue *GV = dyn_cast<GlobalValue>(V);
- if (!GV)
- return false;
+/// X86SelectAddress - Attempt to fill in an address from the given value.
+///
+bool X86FastISel::X86SelectAddress(Value *V, X86AddressMode &AM, bool isCall) {
+ User *U;
+ unsigned Opcode = Instruction::UserOp1;
+ if (Instruction *I = dyn_cast<Instruction>(V)) {
+ Opcode = I->getOpcode();
+ U = I;
+ } else if (ConstantExpr *C = dyn_cast<ConstantExpr>(V)) {
+ Opcode = C->getOpcode();
+ U = C;
+ }
- if (Subtarget->GVRequiresExtraLoad(GV, TM, isCall)) {
- // Issue load from stub if necessary.
- unsigned Opc = 0;
- const TargetRegisterClass *RC = NULL;
- if (TLI.getPointerTy() == MVT::i32) {
- Opc = X86::MOV32rm;
- RC = X86::GR32RegisterClass;
- } else {
- Opc = X86::MOV64rm;
- RC = X86::GR64RegisterClass;
+ switch (Opcode) {
+ default: break;
+ case Instruction::BitCast:
+ // Look past bitcasts.
+ return X86SelectAddress(U->getOperand(0), AM, isCall);
+
+ case Instruction::IntToPtr:
+ // Look past no-op inttoptrs.
+ if (TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy())
+ return X86SelectAddress(U->getOperand(0), AM, isCall);
+
+ case Instruction::PtrToInt:
+ // Look past no-op ptrtoints.
+ if (TLI.getValueType(U->getType()) == TLI.getPointerTy())
+ return X86SelectAddress(U->getOperand(0), AM, isCall);
+
+ case Instruction::Alloca: {
+ if (isCall) break;
+ // Do static allocas.
+ const AllocaInst *A = cast<AllocaInst>(V);
+ DenseMap<const AllocaInst*, int>::iterator SI = StaticAllocaMap.find(A);
+ if (SI != StaticAllocaMap.end()) {
+ AM.BaseType = X86AddressMode::FrameIndexBase;
+ AM.Base.FrameIndex = SI->second;
+ return true;
}
- Op0 = createResultReg(RC);
- X86AddressMode AM;
+ break;
+ }
+
+ case Instruction::Add: {
+ if (isCall) break;
+ // Adds of constants are common and easy enough.
+ if (ConstantInt *CI = dyn_cast<ConstantInt>(U->getOperand(1))) {
+ uint64_t Disp = (int32_t)AM.Disp + (uint64_t)CI->getSExtValue();
+ // They have to fit in the 32-bit signed displacement field though.
+ if (isInt32(Disp)) {
+ AM.Disp = (uint32_t)Disp;
+ return X86SelectAddress(U->getOperand(0), AM, isCall);
+ }
+ }
+ break;
+ }
+
+ case Instruction::GetElementPtr: {
+ if (isCall) break;
+ // Pattern-match simple GEPs.
+ uint64_t Disp = (int32_t)AM.Disp;
+ unsigned IndexReg = AM.IndexReg;
+ unsigned Scale = AM.Scale;
+ gep_type_iterator GTI = gep_type_begin(U);
+ // Look at all but the last index. Constants can be folded,
+ // and one dynamic index can be handled, if the scale is supported.
+ for (User::op_iterator i = U->op_begin() + 1, e = U->op_end();
+ i != e; ++i, ++GTI) {
+ Value *Op = *i;
+ if (const StructType *STy = dyn_cast<StructType>(*GTI)) {
+ const StructLayout *SL = TD.getStructLayout(STy);
+ unsigned Idx = cast<ConstantInt>(Op)->getZExtValue();
+ Disp += SL->getElementOffset(Idx);
+ } else {
+ uint64_t S = TD.getABITypeSize(GTI.getIndexedType());
+ if (ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
+ // Constant-offset addressing.
+ Disp += CI->getSExtValue() * S;
+ } else if (IndexReg == 0 &&
+ (!AM.GV ||
+ !getTargetMachine()->symbolicAddressesAreRIPRel()) &&
+ (S == 1 || S == 2 || S == 4 || S == 8)) {
+ // Scaled-index addressing.
+ Scale = S;
+ IndexReg = getRegForValue(Op);
+ if (IndexReg == 0)
+ return false;
+ } else
+ // Unsupported.
+ goto unsupported_gep;
+ }
+ }
+ // Check for displacement overflow.
+ if (!isInt32(Disp))
+ break;
+ // Ok, the GEP indices were covered by constant-offset and scaled-index
+ // addressing. Update the address state and move on to examining the base.
+ AM.IndexReg = IndexReg;
+ AM.Scale = Scale;
+ AM.Disp = (uint32_t)Disp;
+ return X86SelectAddress(U->getOperand(0), AM, isCall);
+ unsupported_gep:
+ // Ok, the GEP indices weren't all covered.
+ break;
+ }
+ }
+
+ // Handle constant address.
+ if (GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
+ // Can't handle alternate code models yet.
+ if (TM.getCodeModel() != CodeModel::Default &&
+ TM.getCodeModel() != CodeModel::Small)
+ return false;
+
+ // RIP-relative addresses can't have additional register operands.
+ if (getTargetMachine()->symbolicAddressesAreRIPRel() &&
+ (AM.Base.Reg != 0 || AM.IndexReg != 0))
+ return false;
+
+ // Set up the basic address.
AM.GV = GV;
- addFullAddress(BuildMI(MBB, TII.get(Opc), Op0), AM);
- // Prevent loading GV stub multiple times in same MBB.
- LocalValueMap[V] = Op0;
+ if (!isCall &&
+ TM.getRelocationModel() == Reloc::PIC_ &&
+ !Subtarget->is64Bit())
+ AM.Base.Reg = getInstrInfo()->getGlobalBaseReg(&MF);
+
+ // Emit an extra load if the ABI requires it.
+ if (Subtarget->GVRequiresExtraLoad(GV, TM, isCall)) {
+ // Check to see if we've already materialized this
+ // value in a register in this block.
+ if (unsigned Reg = LocalValueMap[V]) {
+ AM.Base.Reg = Reg;
+ AM.GV = 0;
+ return true;
+ }
+ // Issue load from stub if necessary.
+ unsigned Opc = 0;
+ const TargetRegisterClass *RC = NULL;
+ if (TLI.getPointerTy() == MVT::i32) {
+ Opc = X86::MOV32rm;
+ RC = X86::GR32RegisterClass;
+ } else {
+ Opc = X86::MOV64rm;
+ RC = X86::GR64RegisterClass;
+ }
+
+ X86AddressMode StubAM;
+ StubAM.Base.Reg = AM.Base.Reg;
+ StubAM.GV = AM.GV;
+ unsigned ResultReg = createResultReg(RC);
+ addFullAddress(BuildMI(MBB, TII.get(Opc), ResultReg), StubAM);
+
+ // Now construct the final address. Note that the Disp, Scale,
+ // and Index values may already be set here.
+ AM.Base.Reg = ResultReg;
+ AM.GV = 0;
+
+ // Prevent loading GV stub multiple times in same MBB.
+ LocalValueMap[V] = AM.Base.Reg;
+ }
+ return true;
}
- return true;
+
+ // If all else fails, try to materialize the value in a register.
+ if (!AM.GV || !getTargetMachine()->symbolicAddressesAreRIPRel()) {
+ if (AM.Base.Reg == 0) {
+ AM.Base.Reg = getRegForValue(V);
+ return AM.Base.Reg != 0;
+ }
+ if (AM.IndexReg == 0) {
+ assert(AM.Scale == 1 && "Scale with no index!");
+ AM.IndexReg = getRegForValue(V);
+ return AM.IndexReg != 0;
+ }
+ }
+
+ return false;
}
/// X86SelectStore - Select and emit code to implement store instructions.
// Unhandled operand. Halt "fast" selection and bail.
return false;
- Value *V = I->getOperand(1);
- unsigned Ptr = getRegForValue(V);
- if (Ptr == 0) {
- // Handle constant store address.
- if (!isa<Constant>(V) || !X86SelectConstAddr(V, Ptr))
- // Unhandled operand. Halt "fast" selection and bail.
- return false;
- }
+ X86AddressMode AM;
+ if (!X86SelectAddress(I->getOperand(1), AM, false))
+ return false;
- return X86FastEmitStore(VT, Val, Ptr, 0, V);
+ return X86FastEmitStore(VT, Val, AM);
}
/// X86SelectLoad - Select and emit code to implement load instructions.
if (!isTypeLegal(I->getType(), TLI, VT))
return false;
- Value *V = I->getOperand(0);
- unsigned Ptr = getRegForValue(V);
- if (Ptr == 0) {
- // Handle constant load address.
- // FIXME: If load type is something we can't handle, this can result in
- // a dead stub load instruction.
- if (!isa<Constant>(V) || !X86SelectConstAddr(V, Ptr))
- // Unhandled operand. Halt "fast" selection and bail.
- return false;
- }
+ X86AddressMode AM;
+ if (!X86SelectAddress(I->getOperand(0), AM, false))
+ return false;
unsigned ResultReg = 0;
- if (X86FastEmitLoad(VT, Ptr, V, ResultReg)) {
+ if (X86FastEmitLoad(VT, AM, ResultReg)) {
UpdateValueMap(I, ResultReg);
return true;
}
return false;
}
+unsigned X86FastISel::X86ChooseCmpOpcode(MVT VT) {
+ switch (VT.getSimpleVT()) {
+ case MVT::i8: return X86::CMP8rr;
+ case MVT::i16: return X86::CMP16rr;
+ case MVT::i32: return X86::CMP32rr;
+ case MVT::i64: return X86::CMP64rr;
+ case MVT::f32: return X86::UCOMISSrr;
+ case MVT::f64: return X86::UCOMISDrr;
+ default: break;
+ }
+ return 0;
+}
+
bool X86FastISel::X86SelectCmp(Instruction *I) {
CmpInst *CI = cast<CmpInst>(I);
- MVT VT = TLI.getValueType(I->getOperand(0)->getType());
- if (!TLI.isTypeLegal(VT))
+ MVT VT;
+ if (!isTypeLegal(I->getOperand(0)->getType(), TLI, VT))
return false;
unsigned Op0Reg = getRegForValue(CI->getOperand(0));
unsigned Op1Reg = getRegForValue(CI->getOperand(1));
if (Op1Reg == 0) return false;
- unsigned Opc;
- switch (VT.getSimpleVT()) {
- case MVT::i8: Opc = X86::CMP8rr; break;
- case MVT::i16: Opc = X86::CMP16rr; break;
- case MVT::i32: Opc = X86::CMP32rr; break;
- case MVT::i64: Opc = X86::CMP64rr; break;
- case MVT::f32: Opc = X86::UCOMISSrr; break;
- case MVT::f64: Opc = X86::UCOMISDrr; break;
- default: return false;
- }
+ unsigned Opc = X86ChooseCmpOpcode(VT);
unsigned ResultReg = createResultReg(&X86::GR8RegClass);
switch (CI->getPredicate()) {
}
bool X86FastISel::X86SelectBranch(Instruction *I) {
- BranchInst *BI = cast<BranchInst>(I);
// Unconditional branches are selected by tablegen-generated code.
- unsigned OpReg = getRegForValue(BI->getCondition());
- if (OpReg == 0) return false;
+ // Handle a conditional branch.
+ BranchInst *BI = cast<BranchInst>(I);
MachineBasicBlock *TrueMBB = MBBMap[BI->getSuccessor(0)];
MachineBasicBlock *FalseMBB = MBBMap[BI->getSuccessor(1)];
+ // Fold the common case of a conditional branch with a comparison.
+ if (CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
+ if (CI->hasOneUse()) {
+ MVT VT = TLI.getValueType(CI->getOperand(0)->getType());
+ unsigned Opc = X86ChooseCmpOpcode(VT);
+ if (Opc == 0) return false;
+
+ // Try to take advantage of fallthrough opportunities.
+ CmpInst::Predicate Predicate = CI->getPredicate();
+ if (MBB->isLayoutSuccessor(TrueMBB)) {
+ std::swap(TrueMBB, FalseMBB);
+ Predicate = CmpInst::getInversePredicate(Predicate);
+ }
+
+ unsigned Op0Reg = getRegForValue(CI->getOperand(0));
+ if (Op0Reg == 0) return false;
+ unsigned Op1Reg = getRegForValue(CI->getOperand(1));
+ if (Op1Reg == 0) return false;
+
+ switch (Predicate) {
+ case CmpInst::FCMP_OGT:
+ BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
+ BuildMI(MBB, TII.get(X86::JA)).addMBB(TrueMBB);
+ break;
+ case CmpInst::FCMP_OGE:
+ BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
+ BuildMI(MBB, TII.get(X86::JAE)).addMBB(TrueMBB);
+ break;
+ case CmpInst::FCMP_OLT:
+ BuildMI(MBB, TII.get(Opc)).addReg(Op1Reg).addReg(Op0Reg);
+ BuildMI(MBB, TII.get(X86::JA)).addMBB(TrueMBB);
+ break;
+ case CmpInst::FCMP_OLE:
+ BuildMI(MBB, TII.get(Opc)).addReg(Op1Reg).addReg(Op0Reg);
+ BuildMI(MBB, TII.get(X86::JAE)).addMBB(TrueMBB);
+ break;
+ case CmpInst::FCMP_ONE:
+ BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
+ BuildMI(MBB, TII.get(X86::JNE)).addMBB(TrueMBB);
+ break;
+ case CmpInst::FCMP_ORD:
+ BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
+ BuildMI(MBB, TII.get(X86::JNP)).addMBB(TrueMBB);
+ break;
+ case CmpInst::FCMP_UNO:
+ BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
+ BuildMI(MBB, TII.get(X86::JP)).addMBB(TrueMBB);
+ break;
+ case CmpInst::FCMP_UEQ:
+ BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
+ BuildMI(MBB, TII.get(X86::JE)).addMBB(TrueMBB);
+ break;
+ case CmpInst::FCMP_UGT:
+ BuildMI(MBB, TII.get(Opc)).addReg(Op1Reg).addReg(Op0Reg);
+ BuildMI(MBB, TII.get(X86::JB)).addMBB(TrueMBB);
+ break;
+ case CmpInst::FCMP_UGE:
+ BuildMI(MBB, TII.get(Opc)).addReg(Op1Reg).addReg(Op0Reg);
+ BuildMI(MBB, TII.get(X86::JBE)).addMBB(TrueMBB);
+ break;
+ case CmpInst::FCMP_ULT:
+ BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
+ BuildMI(MBB, TII.get(X86::JB)).addMBB(TrueMBB);
+ break;
+ case CmpInst::FCMP_ULE:
+ BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
+ BuildMI(MBB, TII.get(X86::JBE)).addMBB(TrueMBB);
+ break;
+ case CmpInst::ICMP_EQ:
+ BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
+ BuildMI(MBB, TII.get(X86::JE)).addMBB(TrueMBB);
+ break;
+ case CmpInst::ICMP_NE:
+ BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
+ BuildMI(MBB, TII.get(X86::JNE)).addMBB(TrueMBB);
+ break;
+ case CmpInst::ICMP_UGT:
+ BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
+ BuildMI(MBB, TII.get(X86::JA)).addMBB(TrueMBB);
+ break;
+ case CmpInst::ICMP_UGE:
+ BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
+ BuildMI(MBB, TII.get(X86::JAE)).addMBB(TrueMBB);
+ break;
+ case CmpInst::ICMP_ULT:
+ BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
+ BuildMI(MBB, TII.get(X86::JB)).addMBB(TrueMBB);
+ break;
+ case CmpInst::ICMP_ULE:
+ BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
+ BuildMI(MBB, TII.get(X86::JBE)).addMBB(TrueMBB);
+ break;
+ case CmpInst::ICMP_SGT:
+ BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
+ BuildMI(MBB, TII.get(X86::JG)).addMBB(TrueMBB);
+ break;
+ case CmpInst::ICMP_SGE:
+ BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
+ BuildMI(MBB, TII.get(X86::JGE)).addMBB(TrueMBB);
+ break;
+ case CmpInst::ICMP_SLT:
+ BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
+ BuildMI(MBB, TII.get(X86::JL)).addMBB(TrueMBB);
+ break;
+ case CmpInst::ICMP_SLE:
+ BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
+ BuildMI(MBB, TII.get(X86::JLE)).addMBB(TrueMBB);
+ break;
+ default:
+ return false;
+ }
+ MBB->addSuccessor(TrueMBB);
+ FastEmitBranch(FalseMBB);
+ return true;
+ }
+ }
+
+ // Otherwise do a clumsy setcc and re-test it.
+ unsigned OpReg = getRegForValue(BI->getCondition());
+ if (OpReg == 0) return false;
+
BuildMI(MBB, TII.get(X86::TEST8rr)).addReg(OpReg).addReg(OpReg);
- BuildMI(MBB, TII.get(X86::JNE)).addMBB(TrueMBB);
- BuildMI(MBB, TII.get(X86::JMP)).addMBB(FalseMBB);
+ BuildMI(MBB, TII.get(X86::JNE)).addMBB(TrueMBB);
MBB->addSuccessor(TrueMBB);
- MBB->addSuccessor(FalseMBB);
+
+ FastEmitBranch(FalseMBB);
return true;
}
bool X86FastISel::X86SelectShift(Instruction *I) {
- unsigned CReg = 0;
- unsigned Opc = 0;
+ unsigned CReg = 0, OpReg = 0, OpImm = 0;
const TargetRegisterClass *RC = NULL;
if (I->getType() == Type::Int8Ty) {
CReg = X86::CL;
RC = &X86::GR8RegClass;
switch (I->getOpcode()) {
- case Instruction::LShr: Opc = X86::SHR8rCL; break;
- case Instruction::AShr: Opc = X86::SAR8rCL; break;
- case Instruction::Shl: Opc = X86::SHL8rCL; break;
+ case Instruction::LShr: OpReg = X86::SHR8rCL; OpImm = X86::SHR8ri; break;
+ case Instruction::AShr: OpReg = X86::SAR8rCL; OpImm = X86::SAR8ri; break;
+ case Instruction::Shl: OpReg = X86::SHL8rCL; OpImm = X86::SHL8ri; break;
default: return false;
}
} else if (I->getType() == Type::Int16Ty) {
CReg = X86::CX;
RC = &X86::GR16RegClass;
switch (I->getOpcode()) {
- case Instruction::LShr: Opc = X86::SHR16rCL; break;
- case Instruction::AShr: Opc = X86::SAR16rCL; break;
- case Instruction::Shl: Opc = X86::SHL16rCL; break;
+ case Instruction::LShr: OpReg = X86::SHR16rCL; OpImm = X86::SHR16ri; break;
+ case Instruction::AShr: OpReg = X86::SAR16rCL; OpImm = X86::SAR16ri; break;
+ case Instruction::Shl: OpReg = X86::SHL16rCL; OpImm = X86::SHL16ri; break;
default: return false;
}
} else if (I->getType() == Type::Int32Ty) {
CReg = X86::ECX;
RC = &X86::GR32RegClass;
switch (I->getOpcode()) {
- case Instruction::LShr: Opc = X86::SHR32rCL; break;
- case Instruction::AShr: Opc = X86::SAR32rCL; break;
- case Instruction::Shl: Opc = X86::SHL32rCL; break;
+ case Instruction::LShr: OpReg = X86::SHR32rCL; OpImm = X86::SHR32ri; break;
+ case Instruction::AShr: OpReg = X86::SAR32rCL; OpImm = X86::SAR32ri; break;
+ case Instruction::Shl: OpReg = X86::SHL32rCL; OpImm = X86::SHL32ri; break;
default: return false;
}
} else if (I->getType() == Type::Int64Ty) {
CReg = X86::RCX;
RC = &X86::GR64RegClass;
switch (I->getOpcode()) {
- case Instruction::LShr: Opc = X86::SHR64rCL; break;
- case Instruction::AShr: Opc = X86::SAR64rCL; break;
- case Instruction::Shl: Opc = X86::SHL64rCL; break;
+ case Instruction::LShr: OpReg = X86::SHR64rCL; OpImm = X86::SHR64ri; break;
+ case Instruction::AShr: OpReg = X86::SAR64rCL; OpImm = X86::SAR64ri; break;
+ case Instruction::Shl: OpReg = X86::SHL64rCL; OpImm = X86::SHL64ri; break;
default: return false;
}
} else {
}
MVT VT = MVT::getMVT(I->getType(), /*HandleUnknown=*/true);
- if (VT == MVT::Other || !TLI.isTypeLegal(VT))
+ if (VT == MVT::Other || !isTypeLegal(I->getType(), TLI, VT))
return false;
unsigned Op0Reg = getRegForValue(I->getOperand(0));
if (Op0Reg == 0) return false;
+
+ // Fold immediate in shl(x,3).
+ if (ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1))) {
+ unsigned ResultReg = createResultReg(RC);
+ BuildMI(MBB, TII.get(OpImm),
+ ResultReg).addReg(Op0Reg).addImm(CI->getZExtValue());
+ UpdateValueMap(I, ResultReg);
+ return true;
+ }
+
unsigned Op1Reg = getRegForValue(I->getOperand(1));
if (Op1Reg == 0) return false;
TII.copyRegToReg(*MBB, MBB->end(), CReg, Op1Reg, RC, RC);
unsigned ResultReg = createResultReg(RC);
- BuildMI(MBB, TII.get(Opc), ResultReg).addReg(Op0Reg);
+ BuildMI(MBB, TII.get(OpReg), ResultReg).addReg(Op0Reg)
+ // FIXME: The "Local" register allocator's physreg liveness doesn't
+ // recognize subregs. Adding the superreg of CL that's actually defined
+ // prevents it from being re-allocated for this instruction.
+ .addReg(CReg, false, true);
UpdateValueMap(I, ResultReg);
return true;
}
bool X86FastISel::X86SelectSelect(Instruction *I) {
const Type *Ty = I->getType();
if (isa<PointerType>(Ty))
- Ty = TLI.getTargetData()->getIntPtrType();
+ Ty = TD.getIntPtrType();
unsigned Opc = 0;
const TargetRegisterClass *RC = NULL;
}
MVT VT = MVT::getMVT(Ty, /*HandleUnknown=*/true);
- if (VT == MVT::Other || !TLI.isTypeLegal(VT))
+ if (VT == MVT::Other || !isTypeLegal(Ty, TLI, VT))
return false;
unsigned Op0Reg = getRegForValue(I->getOperand(0));
return true;
}
+bool X86FastISel::X86SelectFPExt(Instruction *I) {
+ if (Subtarget->hasSSE2()) {
+ if (I->getType() == Type::DoubleTy) {
+ Value *V = I->getOperand(0);
+ if (V->getType() == Type::FloatTy) {
+ unsigned OpReg = getRegForValue(V);
+ if (OpReg == 0) return false;
+ unsigned ResultReg = createResultReg(X86::FR64RegisterClass);
+ BuildMI(MBB, TII.get(X86::CVTSS2SDrr), ResultReg).addReg(OpReg);
+ UpdateValueMap(I, ResultReg);
+ return true;
+ }
+ }
+ }
+
+ return false;
+}
+
+bool X86FastISel::X86SelectFPTrunc(Instruction *I) {
+ if (Subtarget->hasSSE2()) {
+ if (I->getType() == Type::FloatTy) {
+ Value *V = I->getOperand(0);
+ if (V->getType() == Type::DoubleTy) {
+ unsigned OpReg = getRegForValue(V);
+ if (OpReg == 0) return false;
+ unsigned ResultReg = createResultReg(X86::FR32RegisterClass);
+ BuildMI(MBB, TII.get(X86::CVTSD2SSrr), ResultReg).addReg(OpReg);
+ UpdateValueMap(I, ResultReg);
+ return true;
+ }
+ }
+ }
+
+ return false;
+}
+
bool X86FastISel::X86SelectTrunc(Instruction *I) {
if (Subtarget->is64Bit())
// All other cases should be handled by the tblgen generated code.
return false;
}
- // Materialize callee address in a register. FIXME: GV address can be
- // handled with a CALLpcrel32 instead.
- unsigned CalleeOp = getRegForValue(Callee);
- if (CalleeOp == 0) {
- if (!isa<Constant>(Callee) || !X86SelectConstAddr(Callee, CalleeOp, true))
- // Unhandled operand. Halt "fast" selection and bail.
- return false;
- }
-
// Handle only C and fastcc calling conventions for now.
CallSite CS(CI);
unsigned CC = CS.getCallingConv();
// Handle *simple* calls for now.
const Type *RetTy = CS.getType();
MVT RetVT;
- if (!isTypeLegal(RetTy, TLI, RetVT, true))
+ if (RetTy == Type::VoidTy)
+ RetVT = MVT::isVoid;
+ else if (!isTypeLegal(RetTy, TLI, RetVT, true))
+ return false;
+
+ // Materialize callee address in a register. FIXME: GV address can be
+ // handled with a CALLpcrel32 instead.
+ X86AddressMode CalleeAM;
+ if (!X86SelectAddress(Callee, CalleeAM, true))
+ return false;
+ unsigned CalleeOp = 0;
+ GlobalValue *GV = 0;
+ if (CalleeAM.Base.Reg != 0) {
+ assert(CalleeAM.GV == 0);
+ CalleeOp = CalleeAM.Base.Reg;
+ } else if (CalleeAM.GV != 0) {
+ assert(CalleeAM.GV != 0);
+ GV = CalleeAM.GV;
+ } else
return false;
// Allow calls which produce i1 results.
return false;
ISD::ArgFlagsTy Flags;
unsigned AttrInd = i - CS.arg_begin() + 1;
- if (CS.paramHasAttr(AttrInd, ParamAttr::SExt))
+ if (CS.paramHasAttr(AttrInd, Attribute::SExt))
Flags.setSExt();
- if (CS.paramHasAttr(AttrInd, ParamAttr::ZExt))
+ if (CS.paramHasAttr(AttrInd, Attribute::ZExt))
Flags.setZExt();
// FIXME: Only handle *easy* calls for now.
- if (CS.paramHasAttr(AttrInd, ParamAttr::InReg) ||
- CS.paramHasAttr(AttrInd, ParamAttr::StructRet) ||
- CS.paramHasAttr(AttrInd, ParamAttr::Nest) ||
- CS.paramHasAttr(AttrInd, ParamAttr::ByVal))
+ if (CS.paramHasAttr(AttrInd, Attribute::InReg) ||
+ CS.paramHasAttr(AttrInd, Attribute::StructRet) ||
+ CS.paramHasAttr(AttrInd, Attribute::Nest) ||
+ CS.paramHasAttr(AttrInd, Attribute::ByVal))
return false;
const Type *ArgTy = (*i)->getType();
unsigned NumBytes = CCInfo.getNextStackOffset();
// Issue CALLSEQ_START
- BuildMI(MBB, TII.get(X86::ADJCALLSTACKDOWN)).addImm(NumBytes);
+ unsigned AdjStackDown = TM.getRegisterInfo()->getCallFrameSetupOpcode();
+ BuildMI(MBB, TII.get(AdjStackDown)).addImm(NumBytes);
// Process argumenet: walk the register/memloc assignments, inserting
// copies / loads.
case CCValAssign::AExt: {
bool Emitted = X86FastEmitExtend(ISD::ANY_EXTEND, VA.getLocVT(),
Arg, ArgVT, Arg);
+ if (!Emitted)
+ Emitted = X86FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(),
+ Arg, ArgVT, Arg);
+ if (!Emitted)
+ Emitted = X86FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(),
+ Arg, ArgVT, Arg);
+
assert(Emitted && "Failed to emit a aext!");
ArgVT = VA.getLocVT();
break;
RegArgs.push_back(VA.getLocReg());
} else {
unsigned LocMemOffset = VA.getLocMemOffset();
- X86FastEmitStore(ArgVT, Arg, StackPtr, LocMemOffset, NULL);
+ X86AddressMode AM;
+ AM.Base.Reg = StackPtr;
+ AM.Disp = LocMemOffset;
+ X86FastEmitStore(ArgVT, Arg, AM);
}
}
+ // ELF / PIC requires GOT in the EBX register before function calls via PLT
+ // GOT pointer.
+ if (!Subtarget->is64Bit() &&
+ TM.getRelocationModel() == Reloc::PIC_ &&
+ Subtarget->isPICStyleGOT()) {
+ TargetRegisterClass *RC = X86::GR32RegisterClass;
+ unsigned Base = getInstrInfo()->getGlobalBaseReg(&MF);
+ bool Emitted = TII.copyRegToReg(*MBB, MBB->end(), X86::EBX, Base, RC, RC);
+ assert(Emitted && "Failed to emit a copy instruction!");
+ }
+
// Issue the call.
unsigned CallOpc = CalleeOp
? (Subtarget->is64Bit() ? X86::CALL64r : X86::CALL32r)
: (Subtarget->is64Bit() ? X86::CALL64pcrel32 : X86::CALLpcrel32);
MachineInstrBuilder MIB = CalleeOp
? BuildMI(MBB, TII.get(CallOpc)).addReg(CalleeOp)
- :BuildMI(MBB, TII.get(CallOpc)).addGlobalAddress(cast<GlobalValue>(Callee));
+ : BuildMI(MBB, TII.get(CallOpc)).addGlobalAddress(GV);
+
+ // Add an implicit use GOT pointer in EBX.
+ if (!Subtarget->is64Bit() &&
+ TM.getRelocationModel() == Reloc::PIC_ &&
+ Subtarget->isPICStyleGOT())
+ MIB.addReg(X86::EBX);
+
// Add implicit physical register uses to the call.
while (!RegArgs.empty()) {
MIB.addReg(RegArgs.back());
}
// Issue CALLSEQ_END
- BuildMI(MBB, TII.get(X86::ADJCALLSTACKUP)).addImm(NumBytes).addImm(0);
+ unsigned AdjStackUp = TM.getRegisterInfo()->getCallFrameDestroyOpcode();
+ BuildMI(MBB, TII.get(AdjStackUp)).addImm(NumBytes).addImm(0);
// Now handle call return value (if any).
if (RetVT.getSimpleVT() != MVT::isVoid) {
MVT ResVT = RVLocs[0].getValVT();
unsigned Opc = ResVT == MVT::f32 ? X86::ST_Fp80m32 : X86::ST_Fp80m64;
unsigned MemSize = ResVT.getSizeInBits()/8;
- int FI = MFI->CreateStackObject(MemSize, MemSize);
+ int FI = MFI.CreateStackObject(MemSize, MemSize);
addFrameReference(BuildMI(MBB, TII.get(Opc)), FI).addReg(ResultReg);
DstRC = ResVT == MVT::f32
? X86::FR32RegisterClass : X86::FR64RegisterClass;
return X86SelectSelect(I);
case Instruction::Trunc:
return X86SelectTrunc(I);
+ case Instruction::FPExt:
+ return X86SelectFPExt(I);
+ case Instruction::FPTrunc:
+ return X86SelectFPTrunc(I);
}
return false;
}
-unsigned X86FastISel::TargetMaterializeConstant(Constant *C,
- MachineConstantPool* MCP) {
- // Can't handle PIC-mode yet.
- if (TM.getRelocationModel() == Reloc::PIC_)
- return 0;
-
- MVT VT = MVT::getMVT(C->getType(), /*HandleUnknown=*/true);
- if (VT == MVT::Other || !VT.isSimple())
- // Unhandled type. Halt "fast" selection and bail.
- return false;
- if (VT == MVT::iPTR)
- // Use pointer type.
- VT = TLI.getPointerTy();
- // We only handle legal types. For example, on x86-32 the instruction
- // selector contains all of the 64-bit instructions from x86-64,
- // under the assumption that i64 won't be used if the target doesn't
- // support it.
- if (!TLI.isTypeLegal(VT))
+unsigned X86FastISel::TargetMaterializeConstant(Constant *C) {
+ MVT VT;
+ if (!isTypeLegal(C->getType(), TLI, VT))
return false;
// Get opcode and regclass of the output for the given load instruction.
}
break;
case MVT::f80:
- Opc = X86::LD_Fp80m;
- RC = X86::RFP80RegisterClass;
- break;
+ // No f80 support yet.
+ return false;
}
- unsigned ResultReg = createResultReg(RC);
+ // Materialize addresses with LEA instructions.
if (isa<GlobalValue>(C)) {
- // FIXME: If store value type is something we can't handle, this can result
- // in a dead stub load instruction.
- if (X86SelectConstAddr(C, ResultReg))
+ X86AddressMode AM;
+ if (X86SelectAddress(C, AM, false)) {
+ if (TLI.getPointerTy() == MVT::i32)
+ Opc = X86::LEA32r;
+ else
+ Opc = X86::LEA64r;
+ unsigned ResultReg = createResultReg(RC);
+ addFullAddress(BuildMI(MBB, TII.get(Opc), ResultReg), AM);
return ResultReg;
+ }
return 0;
}
// MachineConstantPool wants an explicit alignment.
- unsigned Align =
- TM.getTargetData()->getPreferredTypeAlignmentShift(C->getType());
+ unsigned Align = TD.getPreferredTypeAlignmentShift(C->getType());
if (Align == 0) {
// Alignment of vector types. FIXME!
- Align = TM.getTargetData()->getABITypeSize(C->getType());
+ Align = TD.getABITypeSize(C->getType());
Align = Log2_64(Align);
}
- unsigned MCPOffset = MCP->getConstantPoolIndex(C, Align);
- addConstantPoolReference(BuildMI(MBB, TII.get(Opc), ResultReg), MCPOffset);
+ // x86-32 PIC requires a PIC base register for constant pools.
+ unsigned PICBase = 0;
+ if (TM.getRelocationModel() == Reloc::PIC_ &&
+ !Subtarget->is64Bit())
+ PICBase = getInstrInfo()->getGlobalBaseReg(&MF);
+
+ // Create the load from the constant pool.
+ unsigned MCPOffset = MCP.getConstantPoolIndex(C, Align);
+ unsigned ResultReg = createResultReg(RC);
+ addConstantPoolReference(BuildMI(MBB, TII.get(Opc), ResultReg), MCPOffset,
+ PICBase);
+
+ return ResultReg;
+}
+
+unsigned X86FastISel::TargetMaterializeAlloca(AllocaInst *C) {
+ // Fail on dynamic allocas. At this point, getRegForValue has already
+ // checked its CSE maps, so if we're here trying to handle a dynamic
+ // alloca, we're not going to succeed. X86SelectAddress has a
+ // check for dynamic allocas, because it's called directly from
+ // various places, but TargetMaterializeAlloca also needs a check
+ // in order to avoid recursion between getRegForValue,
+ // X86SelectAddrss, and TargetMaterializeAlloca.
+ if (!StaticAllocaMap.count(C))
+ return 0;
+
+ X86AddressMode AM;
+ if (!X86SelectAddress(C, AM, false))
+ return 0;
+ unsigned Opc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
+ TargetRegisterClass* RC = TLI.getRegClassFor(TLI.getPointerTy());
+ unsigned ResultReg = createResultReg(RC);
+ addFullAddress(BuildMI(MBB, TII.get(Opc), ResultReg), AM);
return ResultReg;
}
namespace llvm {
llvm::FastISel *X86::createFastISel(MachineFunction &mf,
+ MachineModuleInfo *mmi,
DenseMap<const Value *, unsigned> &vm,
- DenseMap<const BasicBlock *, MachineBasicBlock *> &bm) {
- return new X86FastISel(mf, vm, bm);
+ DenseMap<const BasicBlock *, MachineBasicBlock *> &bm,
+ DenseMap<const AllocaInst *, int> &am) {
+ return new X86FastISel(mf, mmi, vm, bm, am);
}
}
projects / oota-llvm.git / blobdiff