//
//===----------------------------------------------------------------------===//
-#define DEBUG_TYPE "fp"
+#define DEBUG_TYPE "x86-codegen"
#include "X86.h"
#include "X86InstrInfo.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/ADT/STLExtras.h"
#include <algorithm>
-#include <iostream>
#include <set>
using namespace llvm;
-namespace {
- Statistic<> NumFXCH("x86-codegen", "Number of fxch instructions inserted");
- Statistic<> NumFP ("x86-codegen", "Number of floating point instructions");
+STATISTIC(NumFXCH, "Number of fxch instructions inserted");
+STATISTIC(NumFP , "Number of floating point instructions");
+namespace {
struct VISIBILITY_HIDDEN FPS : public MachineFunctionPass {
virtual bool runOnMachineFunction(MachineFunction &MF);
MachineFunctionPass::getAnalysisUsage(AU);
}
private:
- LiveVariables *LV; // Live variable info for current function...
- MachineBasicBlock *MBB; // Current basic block
- unsigned Stack[8]; // FP<n> Registers in each stack slot...
- unsigned RegMap[8]; // Track which stack slot contains each register
- unsigned StackTop; // The current top of the FP stack.
+ const TargetInstrInfo *TII; // Machine instruction info.
+ LiveVariables *LV; // Live variable info for current function...
+ MachineBasicBlock *MBB; // Current basic block
+ unsigned Stack[8]; // FP<n> Registers in each stack slot...
+ unsigned RegMap[8]; // Track which stack slot contains each register
+ unsigned StackTop; // The current top of the FP stack.
void dumpStack() const {
- std::cerr << "Stack contents:";
+ cerr << "Stack contents:";
for (unsigned i = 0; i != StackTop; ++i) {
- std::cerr << " FP" << Stack[i];
+ cerr << " FP" << Stack[i];
assert(RegMap[Stack[i]] == i && "Stack[] doesn't match RegMap[]!");
}
- std::cerr << "\n";
+ cerr << "\n";
}
private:
// getSlot - Return the stack slot number a particular register number is
std::swap(Stack[RegMap[RegOnTop]], Stack[StackTop-1]);
// Emit an fxch to update the runtime processors version of the state
- BuildMI(*MBB, I, X86::FXCH, 1).addReg(STReg);
+ BuildMI(*MBB, I, TII->get(X86::FXCH)).addReg(STReg);
NumFXCH++;
}
}
unsigned STReg = getSTReg(RegNo);
pushReg(AsReg); // New register on top of stack
- BuildMI(*MBB, I, X86::FLDrr, 1).addReg(STReg);
+ BuildMI(*MBB, I, TII->get(X86::FLDrr)).addReg(STReg);
}
// popStackAfter - Pop the current value off of the top of the FP stack
// Early exit.
if (!FPIsUsed) return false;
+ TII = MF.getTarget().getInstrInfo();
LV = &getAnalysis<LiveVariables>();
StackTop = 0;
/// transforming FP instructions into their stack form.
///
bool FPS::processBasicBlock(MachineFunction &MF, MachineBasicBlock &BB) {
- const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
bool Changed = false;
MBB = &BB;
for (MachineBasicBlock::iterator I = BB.begin(); I != BB.end(); ++I) {
MachineInstr *MI = I;
- unsigned Flags = TII.get(MI->getOpcode()).TSFlags;
+ unsigned Flags = MI->getInstrDescriptor()->TSFlags;
if ((Flags & X86II::FPTypeMask) == X86II::NotFP)
continue; // Efficiently ignore non-fp insts!
PrevMI = prior(I);
++NumFP; // Keep track of # of pseudo instrs
- DEBUG(std::cerr << "\nFPInst:\t"; MI->print(std::cerr, &(MF.getTarget())));
+ DOUT << "\nFPInst:\t" << *MI;
// Get dead variables list now because the MI pointer may be deleted as part
// of processing!
for (unsigned i = 0, e = DeadRegs.size(); i != e; ++i) {
unsigned Reg = DeadRegs[i];
if (Reg >= X86::FP0 && Reg <= X86::FP6) {
- DEBUG(std::cerr << "Register FP#" << Reg-X86::FP0 << " is dead!\n");
+ DOUT << "Register FP#" << Reg-X86::FP0 << " is dead!\n";
freeStackSlotAfter(I, Reg-X86::FP0);
}
}
DEBUG(
MachineBasicBlock::iterator PrevI(PrevMI);
if (I == PrevI) {
- std::cerr << "Just deleted pseudo instruction\n";
+ cerr << "Just deleted pseudo instruction\n";
} else {
MachineBasicBlock::iterator Start = I;
// Rewind to first instruction newly inserted.
while (Start != BB.begin() && prior(Start) != PrevI) --Start;
- std::cerr << "Inserted instructions:\n\t";
- Start->print(std::cerr, &MF.getTarget());
+ cerr << "Inserted instructions:\n\t";
+ Start->print(*cerr.stream(), &MF.getTarget());
while (++Start != next(I));
}
dumpStack();
// Check to see if there is a popping version of this instruction...
int Opcode = Lookup(PopTable, ARRAY_SIZE(PopTable), I->getOpcode());
if (Opcode != -1) {
- I->setOpcode(Opcode);
+ I->setInstrDescriptor(TII->get(Opcode));
if (Opcode == X86::FUCOMPPr)
I->RemoveOperand(0);
-
} else { // Insert an explicit pop
- I = BuildMI(*MBB, ++I, X86::FSTPrr, 1).addReg(X86::ST0);
+ I = BuildMI(*MBB, ++I, TII->get(X86::FSTPrr)).addReg(X86::ST0);
}
}
RegMap[TopReg] = OldSlot;
RegMap[FPRegNo] = ~0;
Stack[--StackTop] = ~0;
- I = BuildMI(*MBB, ++I, X86::FSTPrr, 1).addReg(STReg);
+ I = BuildMI(*MBB, ++I, TII->get(X86::FSTPrr)).addReg(STReg);
}
// Change from the pseudo instruction to the concrete instruction.
MI->RemoveOperand(0); // Remove the explicit ST(0) operand
- MI->setOpcode(getConcreteOpcode(MI->getOpcode()));
+ MI->setInstrDescriptor(TII->get(getConcreteOpcode(MI->getOpcode())));
// Result gets pushed on the stack.
pushReg(DestReg);
///
void FPS::handleOneArgFP(MachineBasicBlock::iterator &I) {
MachineInstr *MI = I;
- MachineFunction *MF = MI->getParent()->getParent();
- const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo();
- unsigned NumOps = TII.getNumOperands(MI->getOpcode());
+ unsigned NumOps = MI->getInstrDescriptor()->numOperands;
assert((NumOps == 5 || NumOps == 1) &&
"Can only handle fst* & ftst instructions!");
// Convert from the pseudo instruction to the concrete instruction.
MI->RemoveOperand(NumOps-1); // Remove explicit ST(0) operand
- MI->setOpcode(getConcreteOpcode(MI->getOpcode()));
+ MI->setInstrDescriptor(TII->get(getConcreteOpcode(MI->getOpcode())));
if (MI->getOpcode() == X86::FISTP64m ||
MI->getOpcode() == X86::FISTTP16m ||
///
void FPS::handleOneArgFPRW(MachineBasicBlock::iterator &I) {
MachineInstr *MI = I;
- MachineFunction *MF = MI->getParent()->getParent();
- const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo();
- unsigned NumOps = TII.getNumOperands(MI->getOpcode());
+ unsigned NumOps = MI->getInstrDescriptor()->numOperands;
assert(NumOps >= 2 && "FPRW instructions must have 2 ops!!");
// Is this the last use of the source register?
// Change from the pseudo instruction to the concrete instruction.
MI->RemoveOperand(1); // Drop the source operand.
MI->RemoveOperand(0); // Drop the destination operand.
- MI->setOpcode(getConcreteOpcode(MI->getOpcode()));
+ MI->setInstrDescriptor(TII->get(getConcreteOpcode(MI->getOpcode())));
}
ASSERT_SORTED(ForwardSTiTable); ASSERT_SORTED(ReverseSTiTable);
MachineInstr *MI = I;
- MachineFunction *MF = MI->getParent()->getParent();
- const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo();
- unsigned NumOperands = TII.getNumOperands(MI->getOpcode());
+ unsigned NumOperands = MI->getInstrDescriptor()->numOperands;
assert(NumOperands == 3 && "Illegal TwoArgFP instruction!");
unsigned Dest = getFPReg(MI->getOperand(0));
unsigned Op0 = getFPReg(MI->getOperand(NumOperands-2));
// Replace the old instruction with a new instruction
MBB->remove(I++);
- I = BuildMI(*MBB, I, Opcode, 1).addReg(getSTReg(NotTOS));
+ I = BuildMI(*MBB, I, TII->get(Opcode)).addReg(getSTReg(NotTOS));
// If both operands are killed, pop one off of the stack in addition to
// overwriting the other one.
ASSERT_SORTED(ForwardSTiTable); ASSERT_SORTED(ReverseSTiTable);
MachineInstr *MI = I;
- MachineFunction *MF = MI->getParent()->getParent();
- const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo();
- unsigned NumOperands = TII.getNumOperands(MI->getOpcode());
+ unsigned NumOperands = MI->getInstrDescriptor()->numOperands;
assert(NumOperands == 2 && "Illegal FUCOM* instruction!");
unsigned Op0 = getFPReg(MI->getOperand(NumOperands-2));
unsigned Op1 = getFPReg(MI->getOperand(NumOperands-1));
// Change from the pseudo instruction to the concrete instruction.
MI->getOperand(0).setReg(getSTReg(Op1));
MI->RemoveOperand(1);
- MI->setOpcode(getConcreteOpcode(MI->getOpcode()));
+ MI->setInstrDescriptor(TII->get(getConcreteOpcode(MI->getOpcode())));
// If any of the operands are killed by this instruction, free them.
if (KillsOp0) freeStackSlotAfter(I, Op0);
MI->RemoveOperand(0);
MI->RemoveOperand(1);
MI->getOperand(0).setReg(getSTReg(Op1));
- MI->setOpcode(getConcreteOpcode(MI->getOpcode()));
+ MI->setInstrDescriptor(TII->get(getConcreteOpcode(MI->getOpcode())));
// If we kill the second operand, make sure to pop it from the stack.
if (Op0 != Op1 && KillsOp1) {
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