SDNode *Select(SDOperand N);
bool MatchAddress(SDOperand N, X86ISelAddressMode &AM, bool isRoot = true);
- bool SelectAddr(SDOperand N, SDOperand &Base, SDOperand &Scale,
- SDOperand &Index, SDOperand &Disp);
- bool SelectLEAAddr(SDOperand N, SDOperand &Base, SDOperand &Scale,
- SDOperand &Index, SDOperand &Disp);
- bool SelectScalarSSELoad(SDOperand N, SDOperand &Base, SDOperand &Scale,
+ bool SelectAddr(SDOperand Op, SDOperand N, SDOperand &Base,
+ SDOperand &Scale, SDOperand &Index, SDOperand &Disp);
+ bool SelectLEAAddr(SDOperand Op, SDOperand N, SDOperand &Base,
+ SDOperand &Scale, SDOperand &Index, SDOperand &Disp);
+ bool SelectScalarSSELoad(SDOperand Op, SDOperand Pred,
+ SDOperand N, SDOperand &Base, SDOperand &Scale,
SDOperand &Index, SDOperand &Disp,
SDOperand &InChain, SDOperand &OutChain);
bool TryFoldLoad(SDOperand P, SDOperand N,
// Codegen the basic block.
#ifndef NDEBUG
- DEBUG(std::cerr << "===== Instruction selection begins:\n");
+ DOUT << "===== Instruction selection begins:\n";
Indent = 0;
#endif
DAG.setRoot(SelectRoot(DAG.getRoot()));
#ifndef NDEBUG
- DEBUG(std::cerr << "===== Instruction selection ends:\n");
+ DOUT << "===== Instruction selection ends:\n";
#endif
DAG.RemoveDeadNodes();
// Finally, if we found any FP code, emit the FP_REG_KILL instruction.
if (ContainsFPCode) {
- BuildMI(*BB, BB->getFirstTerminator(), X86::FP_REG_KILL, 0);
+ BuildMI(*BB, BB->getFirstTerminator(),
+ TM.getInstrInfo()->get(X86::FP_REG_KILL));
++NumFPKill;
}
}
/// the main function.
void X86DAGToDAGISel::EmitSpecialCodeForMain(MachineBasicBlock *BB,
MachineFrameInfo *MFI) {
+ const TargetInstrInfo *TII = TM.getInstrInfo();
if (Subtarget->isTargetCygwin())
- BuildMI(BB, X86::CALLpcrel32, 1).addExternalSymbol("__main");
+ BuildMI(BB, TII->get(X86::CALLpcrel32)).addExternalSymbol("__main");
// Switch the FPU to 64-bit precision mode for better compatibility and speed.
int CWFrameIdx = MFI->CreateStackObject(2, 2);
- addFrameReference(BuildMI(BB, X86::FNSTCW16m, 4), CWFrameIdx);
+ addFrameReference(BuildMI(BB, TII->get(X86::FNSTCW16m)), CWFrameIdx);
// Set the high part to be 64-bit precision.
- addFrameReference(BuildMI(BB, X86::MOV8mi, 5),
+ addFrameReference(BuildMI(BB, TII->get(X86::MOV8mi)),
CWFrameIdx, 1).addImm(2);
// Reload the modified control word now.
- addFrameReference(BuildMI(BB, X86::FLDCW16m, 4), CWFrameIdx);
+ addFrameReference(BuildMI(BB, TII->get(X86::FLDCW16m)), CWFrameIdx);
}
void X86DAGToDAGISel::EmitFunctionEntryCode(Function &Fn, MachineFunction &MF) {
break;
}
+ case ISD::TargetConstantPool:
+ if (AM.BaseType == X86ISelAddressMode::RegBase &&
+ AM.Base.Reg.Val == 0 &&
+ AM.CP == 0) {
+ ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(N);
+ AM.CP = CP->getConstVal();
+ AM.Align = CP->getAlignment();
+ AM.Disp += CP->getOffset();
+ return false;
+ }
+ break;
+
+ case ISD::TargetGlobalAddress:
+ if (AM.BaseType == X86ISelAddressMode::RegBase &&
+ AM.Base.Reg.Val == 0 &&
+ AM.GV == 0) {
+ GlobalAddressSDNode *G = cast<GlobalAddressSDNode>(N);
+ AM.GV = G->getGlobal();
+ AM.Disp += G->getOffset();
+ return false;
+ }
+ break;
+
+ case ISD::TargetExternalSymbol:
+ if (isRoot &&
+ AM.BaseType == X86ISelAddressMode::RegBase &&
+ AM.Base.Reg.Val == 0) {
+ ExternalSymbolSDNode *S = cast<ExternalSymbolSDNode>(N.getOperand(0));
+ AM.ES = S->getSymbol();
+ return false;
+ }
+ break;
+
+ case ISD::TargetJumpTable:
+ if (isRoot &&
+ AM.BaseType == X86ISelAddressMode::RegBase &&
+ AM.Base.Reg.Val == 0) {
+ JumpTableSDNode *J = cast<JumpTableSDNode>(N.getOperand(0));
+ AM.JT = J->getIndex();
+ return false;
+ }
+ break;
+
case X86ISD::Wrapper:
// If value is available in a register both base and index components have
// been picked, we can't fit the result available in the register in the
// For X86-64 PIC code, only allow GV / CP + displacement so we can use RIP
// relative addressing mode.
- if ((!Subtarget->is64Bit() || TM.getCodeModel() == CodeModel::Small) &&
- (!Available || (AM.Base.Reg.Val && AM.IndexReg.Val))) {
+ if (Subtarget->is64Bit() && TM.getCodeModel() != CodeModel::Small)
+ break;
+ if (!Available || (AM.Base.Reg.Val && AM.IndexReg.Val)) {
bool isRIP = Subtarget->is64Bit();
- if (isRIP && (AM.Base.Reg.Val || AM.Scale > 1 || AM.IndexReg.Val ||
- AM.BaseType == X86ISelAddressMode::FrameIndexBase))
+ if (isRIP &&
+ (AM.Base.Reg.Val || AM.Scale > 1 || AM.IndexReg.Val ||
+ AM.BaseType == X86ISelAddressMode::FrameIndexBase))
break;
if (ConstantPoolSDNode *CP =
dyn_cast<ConstantPoolSDNode>(N.getOperand(0))) {
AM.CP = CP->getConstVal();
AM.Align = CP->getAlignment();
AM.Disp += CP->getOffset();
- if (isRIP)
- AM.isRIPRel = true;
+ AM.isRIPRel = isRIP;
return false;
}
} else if (GlobalAddressSDNode *G =
if (AM.GV == 0) {
AM.GV = G->getGlobal();
AM.Disp += G->getOffset();
- if (isRIP)
- AM.isRIPRel = true;
+ AM.isRIPRel = isRIP;
return false;
}
} else if (isRoot && isRIP) {
AM.IndexReg = ShVal.Val->getOperand(0);
ConstantSDNode *AddVal =
cast<ConstantSDNode>(ShVal.Val->getOperand(1));
- uint64_t Disp = AM.Disp + AddVal->getValue() << Val;
+ uint64_t Disp = AM.Disp + (AddVal->getValue() << Val);
if (isInt32(Disp))
AM.Disp = Disp;
else
/// SelectAddr - returns true if it is able pattern match an addressing mode.
/// It returns the operands which make up the maximal addressing mode it can
/// match by reference.
-bool X86DAGToDAGISel::SelectAddr(SDOperand N, SDOperand &Base, SDOperand &Scale,
- SDOperand &Index, SDOperand &Disp) {
+bool X86DAGToDAGISel::SelectAddr(SDOperand Op, SDOperand N, SDOperand &Base,
+ SDOperand &Scale, SDOperand &Index,
+ SDOperand &Disp) {
X86ISelAddressMode AM;
if (MatchAddress(N, AM))
return false;
/// SelectScalarSSELoad - Match a scalar SSE load. In particular, we want to
/// match a load whose top elements are either undef or zeros. The load flavor
/// is derived from the type of N, which is either v4f32 or v2f64.
-bool X86DAGToDAGISel::SelectScalarSSELoad(SDOperand N, SDOperand &Base,
+bool X86DAGToDAGISel::SelectScalarSSELoad(SDOperand Op, SDOperand Pred,
+ SDOperand N, SDOperand &Base,
SDOperand &Scale, SDOperand &Index,
SDOperand &Disp, SDOperand &InChain,
SDOperand &OutChain) {
if (N.getOpcode() == ISD::SCALAR_TO_VECTOR) {
InChain = N.getOperand(0).getValue(1);
- if (ISD::isNON_EXTLoad(InChain.Val) && InChain.getValue(0).hasOneUse()) {
+ if (ISD::isNON_EXTLoad(InChain.Val) &&
+ InChain.getValue(0).hasOneUse() &&
+ N.hasOneUse() &&
+ CanBeFoldedBy(N.Val, Pred.Val, Op.Val)) {
LoadSDNode *LD = cast<LoadSDNode>(InChain);
- if (!SelectAddr(LD->getBasePtr(), Base, Scale, Index, Disp))
+ if (!SelectAddr(Op, LD->getBasePtr(), Base, Scale, Index, Disp))
return false;
OutChain = LD->getChain();
return true;
// Okay, this is a zero extending load. Fold it.
LoadSDNode *LD = cast<LoadSDNode>(N.getOperand(1).getOperand(0));
- if (!SelectAddr(LD->getBasePtr(), Base, Scale, Index, Disp))
+ if (!SelectAddr(Op, LD->getBasePtr(), Base, Scale, Index, Disp))
return false;
OutChain = LD->getChain();
InChain = SDOperand(LD, 1);
/// SelectLEAAddr - it calls SelectAddr and determines if the maximal addressing
/// mode it matches can be cost effectively emitted as an LEA instruction.
-bool X86DAGToDAGISel::SelectLEAAddr(SDOperand N, SDOperand &Base,
- SDOperand &Scale,
+bool X86DAGToDAGISel::SelectLEAAddr(SDOperand Op, SDOperand N,
+ SDOperand &Base, SDOperand &Scale,
SDOperand &Index, SDOperand &Disp) {
X86ISelAddressMode AM;
if (MatchAddress(N, AM))
if (ISD::isNON_EXTLoad(N.Val) &&
N.hasOneUse() &&
CanBeFoldedBy(N.Val, P.Val, P.Val))
- return SelectAddr(N.getOperand(1), Base, Scale, Index, Disp);
- return false;
-}
-
-static bool isRegister0(SDOperand Op) {
- if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Op))
- return (R->getReg() == 0);
+ return SelectAddr(P, N.getOperand(1), Base, Scale, Index, Disp);
return false;
}
MachineBasicBlock &FirstMBB = BB->getParent()->front();
MachineBasicBlock::iterator MBBI = FirstMBB.begin();
SSARegMap *RegMap = BB->getParent()->getSSARegMap();
- // FIXME: when we get to LP64, we will need to create the appropriate
- // type of register here.
GlobalBaseReg = RegMap->createVirtualRegister(X86::GR32RegisterClass);
- BuildMI(FirstMBB, MBBI, X86::MovePCtoStack, 0);
- BuildMI(FirstMBB, MBBI, X86::POP32r, 1, GlobalBaseReg);
+ const TargetInstrInfo *TII = TM.getInstrInfo();
+ BuildMI(FirstMBB, MBBI, TII->get(X86::MovePCtoStack));
+ BuildMI(FirstMBB, MBBI, TII->get(X86::POP32r), GlobalBaseReg);
}
return CurDAG->getRegister(GlobalBaseReg, TLI.getPointerTy()).Val;
}
unsigned Opcode = Node->getOpcode();
#ifndef NDEBUG
- DEBUG(std::cerr << std::string(Indent, ' '));
- DEBUG(std::cerr << "Selecting: ");
+ DOUT << std::string(Indent, ' ') << "Selecting: ";
DEBUG(Node->dump(CurDAG));
- DEBUG(std::cerr << "\n");
+ DOUT << "\n";
Indent += 2;
#endif
if (Opcode >= ISD::BUILTIN_OP_END && Opcode < X86ISD::FIRST_NUMBER) {
#ifndef NDEBUG
- DEBUG(std::cerr << std::string(Indent-2, ' '));
- DEBUG(std::cerr << "== ");
+ DOUT << std::string(Indent-2, ' ') << "== ";
DEBUG(Node->dump(CurDAG));
- DEBUG(std::cerr << "\n");
+ DOUT << "\n";
Indent -= 2;
#endif
return NULL; // Already selected.
ReplaceUses(N1.getValue(1), Result.getValue(1));
#ifndef NDEBUG
- DEBUG(std::cerr << std::string(Indent-2, ' '));
- DEBUG(std::cerr << "=> ");
+ DOUT << std::string(Indent-2, ' ') << "=> ";
DEBUG(Result.Val->dump(CurDAG));
- DEBUG(std::cerr << "\n");
+ DOUT << "\n";
Indent -= 2;
#endif
return NULL;
default: assert(0 && "Unsupported VT!");
case MVT::i8:
LoReg = X86::AL; HiReg = X86::AH;
- ClrOpcode = X86::MOV8r0;
+ ClrOpcode = 0;
SExtOpcode = X86::CBW;
break;
case MVT::i16:
SDOperand N0 = Node->getOperand(0);
SDOperand N1 = Node->getOperand(1);
-
- bool foldedLoad = false;
- SDOperand Tmp0, Tmp1, Tmp2, Tmp3;
- foldedLoad = TryFoldLoad(N, N1, Tmp0, Tmp1, Tmp2, Tmp3);
- SDOperand Chain;
- if (foldedLoad) {
- Chain = N1.getOperand(0);
- AddToISelQueue(Chain);
- } else
- Chain = CurDAG->getEntryNode();
-
SDOperand InFlag(0, 0);
- AddToISelQueue(N0);
- Chain = CurDAG->getCopyToReg(Chain, CurDAG->getRegister(LoReg, NVT),
- N0, InFlag);
- InFlag = Chain.getValue(1);
-
- if (isSigned) {
- // Sign extend the low part into the high part.
- InFlag =
- SDOperand(CurDAG->getTargetNode(SExtOpcode, MVT::Flag, InFlag), 0);
- } else {
- // Zero out the high part, effectively zero extending the input.
- SDOperand ClrNode = SDOperand(CurDAG->getTargetNode(ClrOpcode, NVT), 0);
- Chain = CurDAG->getCopyToReg(Chain, CurDAG->getRegister(HiReg, NVT),
- ClrNode, InFlag);
+ if (NVT == MVT::i8 && !isSigned) {
+ // Special case for div8, just use a move with zero extension to AX to
+ // clear the upper 8 bits (AH).
+ SDOperand Tmp0, Tmp1, Tmp2, Tmp3, Move, Chain;
+ if (TryFoldLoad(N, N0, Tmp0, Tmp1, Tmp2, Tmp3)) {
+ SDOperand Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, N0.getOperand(0) };
+ AddToISelQueue(N0.getOperand(0));
+ AddToISelQueue(Tmp0);
+ AddToISelQueue(Tmp1);
+ AddToISelQueue(Tmp2);
+ AddToISelQueue(Tmp3);
+ Move =
+ SDOperand(CurDAG->getTargetNode(X86::MOVZX16rm8, MVT::i16, MVT::Other,
+ Ops, 5), 0);
+ Chain = Move.getValue(1);
+ ReplaceUses(N0.getValue(1), Chain);
+ } else {
+ AddToISelQueue(N0);
+ Move =
+ SDOperand(CurDAG->getTargetNode(X86::MOVZX16rr8, MVT::i16, N0), 0);
+ Chain = CurDAG->getEntryNode();
+ }
+ Chain = CurDAG->getCopyToReg(Chain, X86::AX, Move, InFlag);
InFlag = Chain.getValue(1);
+ } else {
+ AddToISelQueue(N0);
+ InFlag =
+ CurDAG->getCopyToReg(CurDAG->getEntryNode(), LoReg, N0,
+ InFlag).getValue(1);
+ if (isSigned) {
+ // Sign extend the low part into the high part.
+ InFlag =
+ SDOperand(CurDAG->getTargetNode(SExtOpcode, MVT::Flag, InFlag), 0);
+ } else {
+ // Zero out the high part, effectively zero extending the input.
+ SDOperand ClrNode = SDOperand(CurDAG->getTargetNode(ClrOpcode, NVT), 0);
+ InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), HiReg, ClrNode,
+ InFlag).getValue(1);
+ }
}
+ SDOperand Tmp0, Tmp1, Tmp2, Tmp3, Chain;
+ bool foldedLoad = TryFoldLoad(N, N1, Tmp0, Tmp1, Tmp2, Tmp3);
if (foldedLoad) {
+ AddToISelQueue(N1.getOperand(0));
AddToISelQueue(Tmp0);
AddToISelQueue(Tmp1);
AddToISelQueue(Tmp2);
AddToISelQueue(Tmp3);
- SDOperand Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Chain, InFlag };
+ SDOperand Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, N1.getOperand(0), InFlag };
SDNode *CNode =
CurDAG->getTargetNode(MOpc, MVT::Other, MVT::Flag, Ops, 6);
Chain = SDOperand(CNode, 0);
InFlag = SDOperand(CNode, 1);
} else {
AddToISelQueue(N1);
+ Chain = CurDAG->getEntryNode();
InFlag =
SDOperand(CurDAG->getTargetNode(Opc, MVT::Flag, N1, InFlag), 0);
}
- SDOperand Result = CurDAG->getCopyFromReg(Chain, isDiv ? LoReg : HiReg,
- NVT, InFlag);
+ SDOperand Result =
+ CurDAG->getCopyFromReg(Chain, isDiv ? LoReg : HiReg, NVT, InFlag);
ReplaceUses(N.getValue(0), Result);
if (foldedLoad)
ReplaceUses(N1.getValue(1), Result.getValue(1));
#ifndef NDEBUG
- DEBUG(std::cerr << std::string(Indent-2, ' '));
- DEBUG(std::cerr << "=> ");
+ DOUT << std::string(Indent-2, ' ') << "=> ";
DEBUG(Result.Val->dump(CurDAG));
- DEBUG(std::cerr << "\n");
+ DOUT << "\n";
Indent -= 2;
#endif
SDNode *ResNode = CurDAG->getTargetNode(Opc2, NVT, Tmp);
#ifndef NDEBUG
- DEBUG(std::cerr << std::string(Indent-2, ' '));
- DEBUG(std::cerr << "=> ");
+ DOUT << std::string(Indent-2, ' ') << "=> ";
DEBUG(ResNode->dump(CurDAG));
- DEBUG(std::cerr << "\n");
+ DOUT << "\n";
Indent -= 2;
#endif
return ResNode;
SDNode *ResNode = SelectCode(N);
#ifndef NDEBUG
- DEBUG(std::cerr << std::string(Indent-2, ' '));
- DEBUG(std::cerr << "=> ");
+ DOUT << std::string(Indent-2, ' ') << "=> ";
if (ResNode == NULL || ResNode == N.Val)
DEBUG(N.Val->dump(CurDAG));
else
DEBUG(ResNode->dump(CurDAG));
- DEBUG(std::cerr << "\n");
+ DOUT << "\n";
Indent -= 2;
#endif
case 'v': // not offsetable ??
default: return true;
case 'm': // memory
- if (!SelectAddr(Op, Op0, Op1, Op2, Op3))
+ if (!SelectAddr(Op, Op, Op0, Op1, Op2, Op3))
return true;
break;
}
projects / oota-llvm.git / blobdiff