Clean up.

[oota-llvm.git] / lib / Target / X86 / X86ISelDAGToDAG.cpp

diff --git a/lib/Target/X86/X86ISelDAGToDAG.cpp b/lib/Target/X86/X86ISelDAGToDAG.cpp
index 72fb33195d5ccdf991519fcdb608a73125442bb7..09f07d01caa539852a0e386528556f0c4fe015c4 100644 (file)
--- a/lib/Target/X86/X86ISelDAGToDAG.cpp
+++ b/lib/Target/X86/X86ISelDAGToDAG.cpp
@@ -525,7 +525,8 @@ void X86DAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
 
     // Finally, if we found any FP code, emit the FP_REG_KILL instruction.
     if (ContainsFPCode) {
-      BuildMI(*BB, BB->getFirstTerminator(), X86::FP_REG_KILL, 0);
+      BuildMI(*BB, BB->getFirstTerminator(),
+              TM.getInstrInfo()->get(X86::FP_REG_KILL));
       ++NumFPKill;
     }
   }
@@ -535,19 +536,20 @@ void X86DAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
 /// the main function.
 void X86DAGToDAGISel::EmitSpecialCodeForMain(MachineBasicBlock *BB,
                                              MachineFrameInfo *MFI) {
+  const TargetInstrInfo *TII = TM.getInstrInfo();
   if (Subtarget->isTargetCygwin())
-    BuildMI(BB, X86::CALLpcrel32, 1).addExternalSymbol("__main");
+    BuildMI(BB, TII->get(X86::CALLpcrel32)).addExternalSymbol("__main");
 
   // Switch the FPU to 64-bit precision mode for better compatibility and speed.
   int CWFrameIdx = MFI->CreateStackObject(2, 2);
-  addFrameReference(BuildMI(BB, X86::FNSTCW16m, 4), CWFrameIdx);
+  addFrameReference(BuildMI(BB, TII->get(X86::FNSTCW16m)), CWFrameIdx);
 
   // Set the high part to be 64-bit precision.
-  addFrameReference(BuildMI(BB, X86::MOV8mi, 5),
+  addFrameReference(BuildMI(BB, TII->get(X86::MOV8mi)),
                     CWFrameIdx, 1).addImm(2);
 
   // Reload the modified control word now.
-  addFrameReference(BuildMI(BB, X86::FLDCW16m, 4), CWFrameIdx);
+  addFrameReference(BuildMI(BB, TII->get(X86::FLDCW16m)), CWFrameIdx);
 }
 
 void X86DAGToDAGISel::EmitFunctionEntryCode(Function &Fn, MachineFunction &MF) {
@@ -588,6 +590,49 @@ bool X86DAGToDAGISel::MatchAddress(SDOperand N, X86ISelAddressMode &AM,
     break;
   }
 
+  case ISD::TargetConstantPool:
+    if (AM.BaseType == X86ISelAddressMode::RegBase &&
+        AM.Base.Reg.Val == 0 &&
+        AM.CP == 0) {
+      ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(N);
+      AM.CP = CP->getConstVal();
+      AM.Align = CP->getAlignment();
+      AM.Disp += CP->getOffset();
+      return false;
+    }
+    break;
+
+  case ISD::TargetGlobalAddress:
+    if (AM.BaseType == X86ISelAddressMode::RegBase &&
+        AM.Base.Reg.Val == 0 &&
+        AM.GV == 0) {
+      GlobalAddressSDNode *G = cast<GlobalAddressSDNode>(N);
+      AM.GV = G->getGlobal();
+      AM.Disp += G->getOffset();
+      return false;
+    }
+    break;
+
+  case ISD::TargetExternalSymbol:
+    if (isRoot &&
+        AM.BaseType == X86ISelAddressMode::RegBase &&
+        AM.Base.Reg.Val == 0) {
+      ExternalSymbolSDNode *S = cast<ExternalSymbolSDNode>(N.getOperand(0));
+      AM.ES = S->getSymbol();
+      return false;
+    }
+    break;
+
+  case ISD::TargetJumpTable:
+    if (isRoot &&
+        AM.BaseType == X86ISelAddressMode::RegBase &&
+        AM.Base.Reg.Val == 0) {
+      JumpTableSDNode *J = cast<JumpTableSDNode>(N.getOperand(0));
+      AM.JT = J->getIndex();
+      return false;
+    }
+    break;
+
   case X86ISD::Wrapper:
     // If value is available in a register both base and index components have
     // been picked, we can't fit the result available in the register in the
@@ -598,11 +643,13 @@ bool X86DAGToDAGISel::MatchAddress(SDOperand N, X86ISelAddressMode &AM,
 
     // For X86-64 PIC code, only allow GV / CP + displacement so we can use RIP
     // relative addressing mode.
-    if ((!Subtarget->is64Bit() || TM.getCodeModel() == CodeModel::Small) &&
-        (!Available || (AM.Base.Reg.Val && AM.IndexReg.Val))) {
+    if (Subtarget->is64Bit() && TM.getCodeModel() != CodeModel::Small)
+      break;
+    if (!Available || (AM.Base.Reg.Val && AM.IndexReg.Val)) {
       bool isRIP = Subtarget->is64Bit();
-      if (isRIP && (AM.Base.Reg.Val || AM.Scale > 1 || AM.IndexReg.Val ||
-                    AM.BaseType == X86ISelAddressMode::FrameIndexBase))
+      if (isRIP &&
+          (AM.Base.Reg.Val || AM.Scale > 1 || AM.IndexReg.Val ||
+           AM.BaseType == X86ISelAddressMode::FrameIndexBase))
         break;
       if (ConstantPoolSDNode *CP =
           dyn_cast<ConstantPoolSDNode>(N.getOperand(0))) {
@@ -610,8 +657,7 @@ bool X86DAGToDAGISel::MatchAddress(SDOperand N, X86ISelAddressMode &AM,
           AM.CP = CP->getConstVal();
           AM.Align = CP->getAlignment();
           AM.Disp += CP->getOffset();
-          if (isRIP)
-            AM.isRIPRel = true;
+          AM.isRIPRel = isRIP;
           return false;
         }
       } else if (GlobalAddressSDNode *G =
@@ -619,8 +665,7 @@ bool X86DAGToDAGISel::MatchAddress(SDOperand N, X86ISelAddressMode &AM,
         if (AM.GV == 0) {
           AM.GV = G->getGlobal();
           AM.Disp += G->getOffset();
-          if (isRIP)
-            AM.isRIPRel = true;
+          AM.isRIPRel = isRIP;
           return false;
         }
       } else if (isRoot && isRIP) {
@@ -943,11 +988,10 @@ SDNode *X86DAGToDAGISel::getGlobalBaseReg() {
     MachineBasicBlock &FirstMBB = BB->getParent()->front();
     MachineBasicBlock::iterator MBBI = FirstMBB.begin();
     SSARegMap *RegMap = BB->getParent()->getSSARegMap();
-    // FIXME: when we get to LP64, we will need to create the appropriate
-    // type of register here.
     GlobalBaseReg = RegMap->createVirtualRegister(X86::GR32RegisterClass);
-    BuildMI(FirstMBB, MBBI, X86::MovePCtoStack, 0);
-    BuildMI(FirstMBB, MBBI, X86::POP32r, 1, GlobalBaseReg);
+    const TargetInstrInfo *TII = TM.getInstrInfo();
+    BuildMI(FirstMBB, MBBI, TII->get(X86::MovePCtoStack));
+    BuildMI(FirstMBB, MBBI, TII->get(X86::POP32r), GlobalBaseReg);
   }
   return CurDAG->getRegister(GlobalBaseReg, TLI.getPointerTy()).Val;
 }