#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/MathExtras.h"
-#include "llvm/Support/Streams.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/ADT/SmallPtrSet.h"
#include "llvm/ADT/Statistic.h"
X86ISelAddressMode()
: BaseType(RegBase), Scale(1), IndexReg(), Disp(0),
- Segment(), GV(0), CP(0), ES(0), JT(-1), Align(0), SymbolFlags(0) {
+ Segment(), GV(0), CP(0), ES(0), JT(-1), Align(0),
+ SymbolFlags(X86II::MO_NO_FLAG) {
}
bool hasSymbolicDisplacement() const {
}
void dump() {
- cerr << "X86ISelAddressMode " << this << "\n";
- cerr << "Base.Reg ";
- if (Base.Reg.getNode() != 0) Base.Reg.getNode()->dump();
- else cerr << "nul";
- cerr << " Base.FrameIndex " << Base.FrameIndex << "\n";
- cerr << " Scale" << Scale << "\n";
- cerr << "IndexReg ";
- if (IndexReg.getNode() != 0) IndexReg.getNode()->dump();
- else cerr << "nul";
- cerr << " Disp " << Disp << "\n";
- cerr << "GV "; if (GV) GV->dump();
- else cerr << "nul";
- cerr << " CP "; if (CP) CP->dump();
- else cerr << "nul";
- cerr << "\n";
- cerr << "ES "; if (ES) cerr << ES; else cerr << "nul";
- cerr << " JT" << JT << " Align" << Align << "\n";
+ errs() << "X86ISelAddressMode " << this << '\n';
+ errs() << "Base.Reg ";
+ if (Base.Reg.getNode() != 0)
+ Base.Reg.getNode()->dump();
+ else
+ errs() << "nul";
+ errs() << " Base.FrameIndex " << Base.FrameIndex << '\n'
+ << " Scale" << Scale << '\n'
+ << "IndexReg ";
+ if (IndexReg.getNode() != 0)
+ IndexReg.getNode()->dump();
+ else
+ errs() << "nul";
+ errs() << " Disp " << Disp << '\n'
+ << "GV ";
+ if (GV)
+ GV->dump();
+ else
+ errs() << "nul";
+ errs() << " CP ";
+ if (CP)
+ CP->dump();
+ else
+ errs() << "nul";
+ errs() << '\n'
+ << "ES ";
+ if (ES)
+ errs() << ES;
+ else
+ errs() << "nul";
+ errs() << " JT" << JT << " Align" << Align << '\n';
}
};
}
private:
SDNode *Select(SDValue N);
SDNode *SelectAtomic64(SDNode *Node, unsigned Opc);
- SDNode *SelectAtomicLoadAdd(SDNode *Node, MVT NVT);
+ SDNode *SelectAtomicLoadAdd(SDNode *Node, EVT NVT);
bool MatchSegmentBaseAddress(SDValue N, X86ISelAddressMode &AM);
bool MatchLoad(SDValue N, X86ISelAddressMode &AM);
Ops.push_back(Load.getOperand(0));
else
Ops.push_back(TF.getOperand(i));
- CurDAG->UpdateNodeOperands(TF, &Ops[0], Ops.size());
- CurDAG->UpdateNodeOperands(Load, TF, Load.getOperand(1), Load.getOperand(2));
- CurDAG->UpdateNodeOperands(Store, Load.getValue(1), Store.getOperand(1),
+ SDValue NewTF = CurDAG->UpdateNodeOperands(TF, &Ops[0], Ops.size());
+ SDValue NewLoad = CurDAG->UpdateNodeOperands(Load, NewTF,
+ Load.getOperand(1),
+ Load.getOperand(2));
+ CurDAG->UpdateNodeOperands(Store, NewLoad.getValue(1), Store.getOperand(1),
Store.getOperand(2), Store.getOperand(3));
}
// If the source and destination are SSE registers, then this is a legal
// conversion that should not be lowered.
- MVT SrcVT = N->getOperand(0).getValueType();
- MVT DstVT = N->getValueType(0);
+ EVT SrcVT = N->getOperand(0).getValueType();
+ EVT DstVT = N->getValueType(0);
bool SrcIsSSE = X86Lowering.isScalarFPTypeInSSEReg(SrcVT);
bool DstIsSSE = X86Lowering.isScalarFPTypeInSSEReg(DstVT);
if (SrcIsSSE && DstIsSSE)
// Here we could have an FP stack truncation or an FPStack <-> SSE convert.
// FPStack has extload and truncstore. SSE can fold direct loads into other
// operations. Based on this, decide what we want to do.
- MVT MemVT;
+ EVT MemVT;
if (N->getOpcode() == ISD::FP_ROUND)
MemVT = DstVT; // FP_ROUND must use DstVT, we can't do a 'trunc load'.
else
// Under X86-64 non-small code model, GV (and friends) are 64-bits, so
// they cannot be folded into immediate fields.
// FIXME: This can be improved for kernel and other models?
- (M == CodeModel::Small || CodeModel::Kernel) &&
+ (M == CodeModel::Small || M == CodeModel::Kernel) &&
// Base and index reg must be 0 in order to use %rip as base and lowering
// must allow RIP.
!AM.hasBaseOrIndexReg() && N.getOpcode() == X86ISD::WrapperRIP) {
AM.Scale = 1;
}
+ // Post-processing: Convert foo to foo(%rip), even in non-PIC mode,
+ // because it has a smaller encoding.
+ // TODO: Which other code models can use this?
+ if (TM.getCodeModel() == CodeModel::Small &&
+ Subtarget->is64Bit() &&
+ AM.Scale == 1 &&
+ AM.BaseType == X86ISelAddressMode::RegBase &&
+ AM.Base.Reg.getNode() == 0 &&
+ AM.IndexReg.getNode() == 0 &&
+ AM.SymbolFlags == X86II::MO_NO_FLAG &&
+ AM.hasSymbolicDisplacement())
+ AM.Base.Reg = CurDAG->getRegister(X86::RIP, MVT::i64);
+
return false;
}
unsigned Depth) {
bool is64Bit = Subtarget->is64Bit();
DebugLoc dl = N.getDebugLoc();
- DEBUG(errs() << "MatchAddress: "); DEBUG(AM.dump());
+ DEBUG({
+ errs() << "MatchAddress: ";
+ AM.dump();
+ });
// Limit recursion.
if (Depth > 5)
return MatchAddressBase(N, AM);
if (!Done && MatchAddress(N, AM))
return false;
- MVT VT = N.getValueType();
+ EVT VT = N.getValueType();
if (AM.BaseType == X86ISelAddressMode::RegBase) {
if (!AM.Base.Reg.getNode())
AM.Base.Reg = CurDAG->getRegister(0, VT);
assert (T == AM.Segment);
AM.Segment = Copy;
- MVT VT = N.getValueType();
+ EVT VT = N.getValueType();
unsigned Complexity = 0;
if (AM.BaseType == X86ISelAddressMode::RegBase)
if (AM.Base.Reg.getNode())
array_lengthof(Ops));
}
-SDNode *X86DAGToDAGISel::SelectAtomicLoadAdd(SDNode *Node, MVT NVT) {
+SDNode *X86DAGToDAGISel::SelectAtomicLoadAdd(SDNode *Node, EVT NVT) {
if (Node->hasAnyUseOfValue(0))
return 0;
}
unsigned Opc = 0;
- switch (NVT.getSimpleVT()) {
+ switch (NVT.getSimpleVT().SimpleTy) {
default: return 0;
case MVT::i8:
if (isInc)
SDNode *X86DAGToDAGISel::Select(SDValue N) {
SDNode *Node = N.getNode();
- MVT NVT = Node->getValueType(0);
+ EVT NVT = Node->getValueType(0);
unsigned Opc, MOpc;
unsigned Opcode = Node->getOpcode();
DebugLoc dl = Node->getDebugLoc();
#ifndef NDEBUG
- DEBUG(errs() << std::string(Indent, ' ') << "Selecting: ");
- DEBUG(Node->dump(CurDAG));
- DEBUG(errs() << "\n");
+ DEBUG({
+ errs() << std::string(Indent, ' ') << "Selecting: ";
+ Node->dump(CurDAG);
+ errs() << '\n';
+ });
Indent += 2;
#endif
if (Node->isMachineOpcode()) {
#ifndef NDEBUG
- DEBUG(errs() << std::string(Indent-2, ' ') << "== ");
- DEBUG(Node->dump(CurDAG));
- DEBUG(errs() << "\n");
+ DEBUG({
+ errs() << std::string(Indent-2, ' ') << "== ";
+ Node->dump(CurDAG);
+ errs() << '\n';
+ });
Indent -= 2;
#endif
return NULL; // Already selected.
SDValue N1 = Node->getOperand(1);
bool isSigned = Opcode == ISD::SMUL_LOHI;
- if (!isSigned)
- switch (NVT.getSimpleVT()) {
+ if (!isSigned) {
+ switch (NVT.getSimpleVT().SimpleTy) {
default: llvm_unreachable("Unsupported VT!");
case MVT::i8: Opc = X86::MUL8r; MOpc = X86::MUL8m; break;
case MVT::i16: Opc = X86::MUL16r; MOpc = X86::MUL16m; break;
case MVT::i32: Opc = X86::MUL32r; MOpc = X86::MUL32m; break;
case MVT::i64: Opc = X86::MUL64r; MOpc = X86::MUL64m; break;
}
- else
- switch (NVT.getSimpleVT()) {
+ } else {
+ switch (NVT.getSimpleVT().SimpleTy) {
default: llvm_unreachable("Unsupported VT!");
case MVT::i8: Opc = X86::IMUL8r; MOpc = X86::IMUL8m; break;
case MVT::i16: Opc = X86::IMUL16r; MOpc = X86::IMUL16m; break;
case MVT::i32: Opc = X86::IMUL32r; MOpc = X86::IMUL32m; break;
case MVT::i64: Opc = X86::IMUL64r; MOpc = X86::IMUL64m; break;
}
+ }
unsigned LoReg, HiReg;
- switch (NVT.getSimpleVT()) {
+ switch (NVT.getSimpleVT().SimpleTy) {
default: llvm_unreachable("Unsupported VT!");
case MVT::i8: LoReg = X86::AL; HiReg = X86::AH; break;
case MVT::i16: LoReg = X86::AX; HiReg = X86::DX; break;
SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
bool foldedLoad = TryFoldLoad(N, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
- // multiplty is commmutative
+ // Multiply is commmutative.
if (!foldedLoad) {
foldedLoad = TryFoldLoad(N, N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
if (foldedLoad)
InFlag = Result.getValue(2);
ReplaceUses(N.getValue(0), Result);
#ifndef NDEBUG
- DEBUG(errs() << std::string(Indent-2, ' ') << "=> ");
- DEBUG(Result.getNode()->dump(CurDAG));
- DEBUG(errs() << "\n");
+ DEBUG({
+ errs() << std::string(Indent-2, ' ') << "=> ";
+ Result.getNode()->dump(CurDAG);
+ errs() << '\n';
+ });
#endif
}
// Copy the high half of the result, if it is needed.
Result,
CurDAG->getTargetConstant(8, MVT::i8)), 0);
// Then truncate it down to i8.
- SDValue SRIdx = CurDAG->getTargetConstant(X86::SUBREG_8BIT, MVT::i32);
- Result = SDValue(CurDAG->getTargetNode(X86::EXTRACT_SUBREG, dl,
- MVT::i8, Result, SRIdx), 0);
+ Result = CurDAG->getTargetExtractSubreg(X86::SUBREG_8BIT, dl,
+ MVT::i8, Result);
} else {
Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
HiReg, NVT, InFlag);
}
ReplaceUses(N.getValue(1), Result);
#ifndef NDEBUG
- DEBUG(errs() << std::string(Indent-2, ' ') << "=> ");
- DEBUG(Result.getNode()->dump(CurDAG));
- DEBUG(errs() << "\n");
+ DEBUG({
+ errs() << std::string(Indent-2, ' ') << "=> ";
+ Result.getNode()->dump(CurDAG);
+ errs() << '\n';
+ });
#endif
}
SDValue N1 = Node->getOperand(1);
bool isSigned = Opcode == ISD::SDIVREM;
- if (!isSigned)
- switch (NVT.getSimpleVT()) {
+ if (!isSigned) {
+ switch (NVT.getSimpleVT().SimpleTy) {
default: llvm_unreachable("Unsupported VT!");
case MVT::i8: Opc = X86::DIV8r; MOpc = X86::DIV8m; break;
case MVT::i16: Opc = X86::DIV16r; MOpc = X86::DIV16m; break;
case MVT::i32: Opc = X86::DIV32r; MOpc = X86::DIV32m; break;
case MVT::i64: Opc = X86::DIV64r; MOpc = X86::DIV64m; break;
}
- else
- switch (NVT.getSimpleVT()) {
+ } else {
+ switch (NVT.getSimpleVT().SimpleTy) {
default: llvm_unreachable("Unsupported VT!");
case MVT::i8: Opc = X86::IDIV8r; MOpc = X86::IDIV8m; break;
case MVT::i16: Opc = X86::IDIV16r; MOpc = X86::IDIV16m; break;
case MVT::i32: Opc = X86::IDIV32r; MOpc = X86::IDIV32m; break;
case MVT::i64: Opc = X86::IDIV64r; MOpc = X86::IDIV64m; break;
}
+ }
unsigned LoReg, HiReg;
unsigned ClrOpcode, SExtOpcode;
- switch (NVT.getSimpleVT()) {
+ switch (NVT.getSimpleVT().SimpleTy) {
default: llvm_unreachable("Unsupported VT!");
case MVT::i8:
LoReg = X86::AL; HiReg = X86::AH;
InFlag = Result.getValue(2);
ReplaceUses(N.getValue(0), Result);
#ifndef NDEBUG
- DEBUG(errs() << std::string(Indent-2, ' ') << "=> ");
- DEBUG(Result.getNode()->dump(CurDAG));
- DEBUG(errs() << "\n");
+ DEBUG({
+ errs() << std::string(Indent-2, ' ') << "=> ";
+ Result.getNode()->dump(CurDAG);
+ errs() << '\n';
+ });
#endif
}
// Copy the remainder (high) result, if it is needed.
CurDAG->getTargetConstant(8, MVT::i8)),
0);
// Then truncate it down to i8.
- SDValue SRIdx = CurDAG->getTargetConstant(X86::SUBREG_8BIT, MVT::i32);
- Result = SDValue(CurDAG->getTargetNode(X86::EXTRACT_SUBREG, dl,
- MVT::i8, Result, SRIdx), 0);
+ Result = CurDAG->getTargetExtractSubreg(X86::SUBREG_8BIT, dl,
+ MVT::i8, Result);
} else {
Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
HiReg, NVT, InFlag);
}
ReplaceUses(N.getValue(1), Result);
#ifndef NDEBUG
- DEBUG(errs() << std::string(Indent-2, ' ') << "=> ");
- DEBUG(Result.getNode()->dump(CurDAG));
- DEBUG(errs() << "\n");
+ DEBUG({
+ errs() << std::string(Indent-2, ' ') << "=> ";
+ Result.getNode()->dump(CurDAG);
+ errs() << '\n';
+ });
#endif
}
return NULL;
}
- case ISD::DECLARE: {
- // Handle DECLARE nodes here because the second operand may have been
- // wrapped in X86ISD::Wrapper.
- SDValue Chain = Node->getOperand(0);
+ case X86ISD::CMP: {
+ SDValue N0 = Node->getOperand(0);
SDValue N1 = Node->getOperand(1);
- SDValue N2 = Node->getOperand(2);
- FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N1);
- // FIXME: We need to handle this for VLAs.
- if (!FINode) {
- ReplaceUses(N.getValue(0), Chain);
- return NULL;
- }
+ // Look for (X86cmp (and $op, $imm), 0) and see if we can convert it to
+ // use a smaller encoding.
+ if (N0.getNode()->getOpcode() == ISD::AND && N0.getNode()->hasOneUse() &&
+ N0.getValueType() != MVT::i8 &&
+ X86::isZeroNode(N1)) {
+ ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getNode()->getOperand(1));
+ if (!C) break;
+
+ // For example, convert "testl %eax, $8" to "testb %al, $8"
+ if ((C->getZExtValue() & ~UINT64_C(0xff)) == 0) {
+ SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i8);
+ SDValue Reg = N0.getNode()->getOperand(0);
+
+ // On x86-32, only the ABCD registers have 8-bit subregisters.
+ if (!Subtarget->is64Bit()) {
+ TargetRegisterClass *TRC = 0;
+ switch (N0.getValueType().getSimpleVT().SimpleTy) {
+ case MVT::i32: TRC = &X86::GR32_ABCDRegClass; break;
+ case MVT::i16: TRC = &X86::GR16_ABCDRegClass; break;
+ default: llvm_unreachable("Unsupported TEST operand type!");
+ }
+ SDValue RC = CurDAG->getTargetConstant(TRC->getID(), MVT::i32);
+ Reg = SDValue(CurDAG->getTargetNode(X86::COPY_TO_REGCLASS, dl,
+ Reg.getValueType(), Reg, RC), 0);
+ }
- if (N2.getOpcode() == ISD::ADD &&
- N2.getOperand(0).getOpcode() == X86ISD::GlobalBaseReg)
- N2 = N2.getOperand(1);
+ // Extract the l-register.
+ SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::SUBREG_8BIT, dl,
+ MVT::i8, Reg);
- // If N2 is not Wrapper(decriptor) then the llvm.declare is mangled
- // somehow, just ignore it.
- if (N2.getOpcode() != X86ISD::Wrapper &&
- N2.getOpcode() != X86ISD::WrapperRIP) {
- ReplaceUses(N.getValue(0), Chain);
- return NULL;
- }
- GlobalAddressSDNode *GVNode =
- dyn_cast<GlobalAddressSDNode>(N2.getOperand(0));
- if (GVNode == 0) {
- ReplaceUses(N.getValue(0), Chain);
- return NULL;
+ // Emit a testb.
+ return CurDAG->getTargetNode(X86::TEST8ri, dl, MVT::i32, Subreg, Imm);
+ }
+
+ // For example, "testl %eax, $2048" to "testb %ah, $8".
+ if ((C->getZExtValue() & ~UINT64_C(0xff00)) == 0) {
+ // Shift the immediate right by 8 bits.
+ SDValue ShiftedImm = CurDAG->getTargetConstant(C->getZExtValue() >> 8,
+ MVT::i8);
+ SDValue Reg = N0.getNode()->getOperand(0);
+
+ // Put the value in an ABCD register.
+ TargetRegisterClass *TRC = 0;
+ switch (N0.getValueType().getSimpleVT().SimpleTy) {
+ case MVT::i64: TRC = &X86::GR64_ABCDRegClass; break;
+ case MVT::i32: TRC = &X86::GR32_ABCDRegClass; break;
+ case MVT::i16: TRC = &X86::GR16_ABCDRegClass; break;
+ default: llvm_unreachable("Unsupported TEST operand type!");
+ }
+ SDValue RC = CurDAG->getTargetConstant(TRC->getID(), MVT::i32);
+ Reg = SDValue(CurDAG->getTargetNode(X86::COPY_TO_REGCLASS, dl,
+ Reg.getValueType(), Reg, RC), 0);
+
+ // Extract the h-register.
+ SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::SUBREG_8BIT_HI, dl,
+ MVT::i8, Reg);
+
+ // Emit a testb. No special NOREX tricks are needed since there's
+ // only one GPR operand!
+ return CurDAG->getTargetNode(X86::TEST8ri, dl, MVT::i32,
+ Subreg, ShiftedImm);
+ }
+
+ // For example, "testl %eax, $32776" to "testw %ax, $32776".
+ if ((C->getZExtValue() & ~UINT64_C(0xffff)) == 0 &&
+ N0.getValueType() != MVT::i16) {
+ SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i16);
+ SDValue Reg = N0.getNode()->getOperand(0);
+
+ // Extract the 16-bit subregister.
+ SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::SUBREG_16BIT, dl,
+ MVT::i16, Reg);
+
+ // Emit a testw.
+ return CurDAG->getTargetNode(X86::TEST16ri, dl, MVT::i32, Subreg, Imm);
+ }
+
+ // For example, "testq %rax, $268468232" to "testl %eax, $268468232".
+ if ((C->getZExtValue() & ~UINT64_C(0xffffffff)) == 0 &&
+ N0.getValueType() == MVT::i64) {
+ SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i32);
+ SDValue Reg = N0.getNode()->getOperand(0);
+
+ // Extract the 32-bit subregister.
+ SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::SUBREG_32BIT, dl,
+ MVT::i32, Reg);
+
+ // Emit a testl.
+ return CurDAG->getTargetNode(X86::TEST32ri, dl, MVT::i32, Subreg, Imm);
+ }
}
- SDValue Tmp1 = CurDAG->getTargetFrameIndex(FINode->getIndex(),
- TLI.getPointerTy());
- SDValue Tmp2 = CurDAG->getTargetGlobalAddress(GVNode->getGlobal(),
- TLI.getPointerTy());
- SDValue Ops[] = { Tmp1, Tmp2, Chain };
- return CurDAG->getTargetNode(TargetInstrInfo::DECLARE, dl,
- MVT::Other, Ops,
- array_lengthof(Ops));
+ break;
}
}
SDNode *ResNode = SelectCode(N);
#ifndef NDEBUG
- DEBUG(errs() << std::string(Indent-2, ' ') << "=> ");
- if (ResNode == NULL || ResNode == N.getNode())
- DEBUG(N.getNode()->dump(CurDAG));
- else
- DEBUG(ResNode->dump(CurDAG));
- DEBUG(errs() << "\n");
+ DEBUG({
+ errs() << std::string(Indent-2, ' ') << "=> ";
+ if (ResNode == NULL || ResNode == N.getNode())
+ N.getNode()->dump(CurDAG);
+ else
+ ResNode->dump(CurDAG);
+ errs() << '\n';
+ });
Indent -= 2;
#endif
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