Introduce a new technique for merging BasicBlock with Instruction sentinel by superpo...

[oota-llvm.git] / lib / Target / X86 / X86ISelDAGToDAG.cpp

diff --git a/lib/Target/X86/X86ISelDAGToDAG.cpp b/lib/Target/X86/X86ISelDAGToDAG.cpp
index d61e3436e945a5117a13580b66a155b45b73041c..855c890120b2e4eec925da98027b8616e457c31c 100644 (file)
--- a/lib/Target/X86/X86ISelDAGToDAG.cpp
+++ b/lib/Target/X86/X86ISelDAGToDAG.cpp
@@ -76,6 +76,11 @@ namespace {
       : BaseType(RegBase), isRIPRel(false), Scale(1), IndexReg(), Disp(0),
         GV(0), CP(0), ES(0), JT(-1), Align(0) {
     }
+
+    bool hasSymbolicDisplacement() const {
+      return GV != 0 || CP != 0 || ES != 0 || JT != -1;
+    }
+
     void dump() {
       cerr << "X86ISelAddressMode " << this << "\n";
       cerr << "Base.Reg ";
@@ -441,7 +446,8 @@ static void MoveBelowCallSeqStart(SelectionDAG *CurDAG, SDValue Load,
       else
         Ops.push_back(Chain.getOperand(i));
     SDValue NewChain =
-      CurDAG->getNode(ISD::TokenFactor, MVT::Other, &Ops[0], Ops.size());
+      CurDAG->getNode(ISD::TokenFactor, Load.getDebugLoc(),
+                      MVT::Other, &Ops[0], Ops.size());
     Ops.clear();
     Ops.push_back(NewChain);
   }
@@ -714,7 +720,8 @@ void X86DAGToDAGISel::EmitSpecialCodeForMain(MachineBasicBlock *BB,
                                              MachineFrameInfo *MFI) {
   const TargetInstrInfo *TII = TM.getInstrInfo();
   if (Subtarget->isTargetCygMing())
-    BuildMI(BB, TII->get(X86::CALLpcrel32)).addExternalSymbol("__main");
+    BuildMI(BB, DebugLoc::getUnknownLoc(),
+            TII->get(X86::CALLpcrel32)).addExternalSymbol("__main");
 }
 
 void X86DAGToDAGISel::EmitFunctionEntryCode(Function &Fn, MachineFunction &MF) {
@@ -730,7 +737,7 @@ void X86DAGToDAGISel::EmitFunctionEntryCode(Function &Fn, MachineFunction &MF) {
 bool X86DAGToDAGISel::MatchAddress(SDValue N, X86ISelAddressMode &AM,
                                    bool isRoot, unsigned Depth) {
   bool is64Bit = Subtarget->is64Bit();
-  DebugLoc dl = N.getNode()->getDebugLoc();
+  DebugLoc dl = N.getDebugLoc();
   DOUT << "MatchAddress: "; DEBUG(AM.dump());
   // Limit recursion.
   if (Depth > 5)
@@ -767,7 +774,7 @@ bool X86DAGToDAGISel::MatchAddress(SDValue N, X86ISelAddressMode &AM,
     if (is64Bit && (TM.getCodeModel() != CodeModel::Small ||
                     AM.Base.Reg.getNode() || AM.IndexReg.getNode()))
       break;
-    if (AM.GV != 0 || AM.CP != 0 || AM.ES != 0 || AM.JT != -1)
+    if (AM.hasSymbolicDisplacement())
       break;
     // If value is available in a register both base and index components have
     // been picked, we can't fit the result available in the register in the
@@ -1113,7 +1120,7 @@ bool X86DAGToDAGISel::SelectLEAAddr(SDValue Op, SDValue N,
   // optimal (especially for code size consideration). LEA is nice because of
   // its three-address nature. Tweak the cost function again when we can run
   // convertToThreeAddress() at register allocation time.
-  if (AM.GV || AM.CP || AM.ES || AM.JT != -1) {
+  if (AM.hasSymbolicDisplacement()) {
     // For X86-64, we should always use lea to materialize RIP relative
     // addresses.
     if (Subtarget->is64Bit())
@@ -1167,7 +1174,7 @@ SDNode *X86DAGToDAGISel::getTruncateTo8Bit(SDValue N0) {
   assert(!Subtarget->is64Bit() &&
          "getTruncateTo8Bit is only needed on x86-32!");
   SDValue SRIdx = CurDAG->getTargetConstant(1, MVT::i32); // SubRegSet 1
-  DebugLoc dl = N0.getNode()->getDebugLoc();
+  DebugLoc dl = N0.getDebugLoc();
 
   // Ensure that the source register has an 8-bit subreg on 32-bit targets
   unsigned Opc;
@@ -1557,17 +1564,29 @@ SDNode *X86DAGToDAGISel::Select(SDValue N) {
       SDValue N1 = Node->getOperand(1);
       SDValue N2 = Node->getOperand(2);
       FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N1);
-      if (!FINode)
-        break;
+      
+      // FIXME: We need to handle this for VLAs.
+      if (!FINode) {
+        ReplaceUses(N.getValue(0), Chain);
+        return NULL;
+      }
+      
       if (N2.getOpcode() == ISD::ADD &&
           N2.getOperand(0).getOpcode() == X86ISD::GlobalBaseReg)
         N2 = N2.getOperand(1);
-      if (N2.getOpcode() != X86ISD::Wrapper)
-        break;
+      
+      // If N2 is not Wrapper(decriptor) then the llvm.declare is mangled
+      // somehow, just ignore it.
+      if (N2.getOpcode() != X86ISD::Wrapper) {
+        ReplaceUses(N.getValue(0), Chain);
+        return NULL;
+      }
       GlobalAddressSDNode *GVNode =
         dyn_cast<GlobalAddressSDNode>(N2.getOperand(0));
-      if (!GVNode)
-        break;
+      if (GVNode == 0) {
+        ReplaceUses(N.getValue(0), Chain);
+        return NULL;
+      }
       SDValue Tmp1 = CurDAG->getTargetFrameIndex(FINode->getIndex(),
                                                  TLI.getPointerTy());
       SDValue Tmp2 = CurDAG->getTargetGlobalAddress(GVNode->getGlobal(),
@@ -1575,7 +1594,6 @@ SDNode *X86DAGToDAGISel::Select(SDValue N) {
       SDValue Ops[] = { Tmp1, Tmp2, Chain };
       return CurDAG->getTargetNode(TargetInstrInfo::DECLARE, dl,
                                    MVT::Other, Ops, 3);
-      break;
     }
   }