#include "llvm/Instructions.h"
#include "llvm/Intrinsics.h"
#include "llvm/Support/CFG.h"
+#include "llvm/Type.h"
#include "llvm/CodeGen/MachineConstantPool.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/ADT/Statistic.h"
-#include <iostream>
#include <queue>
#include <set>
using namespace llvm;
+STATISTIC(NumFPKill , "Number of FP_REG_KILL instructions added");
+STATISTIC(NumLoadMoved, "Number of loads moved below TokenFactor");
+
+
//===----------------------------------------------------------------------===//
// Pattern Matcher Implementation
//===----------------------------------------------------------------------===//
}
namespace {
- Statistic<>
- NumFPKill("x86-codegen", "Number of FP_REG_KILL instructions added");
-
- Statistic<>
- NumLoadMoved("x86-codegen", "Number of loads moved below TokenFactor");
-
//===--------------------------------------------------------------------===//
/// ISel - X86 specific code to select X86 machine instructions for
/// SelectionDAG operations.
private:
SDNode *Select(SDOperand N);
- bool MatchAddress(SDOperand N, X86ISelAddressMode &AM, bool isRoot = true);
+ bool MatchAddress(SDOperand N, X86ISelAddressMode &AM,
+ bool isRoot = true, unsigned Depth = 0);
bool SelectAddr(SDOperand Op, SDOperand N, SDOperand &Base,
SDOperand &Scale, SDOperand &Index, SDOperand &Disp);
bool SelectLEAAddr(SDOperand Op, SDOperand N, SDOperand &Base,
void X86DAGToDAGISel::EmitSpecialCodeForMain(MachineBasicBlock *BB,
MachineFrameInfo *MFI) {
const TargetInstrInfo *TII = TM.getInstrInfo();
- if (Subtarget->isTargetCygwin())
+ if (Subtarget->isTargetCygMing())
BuildMI(BB, TII->get(X86::CALLpcrel32)).addExternalSymbol("__main");
// Switch the FPU to 64-bit precision mode for better compatibility and speed.
/// returning true if it cannot be done. This just pattern matches for the
/// addressing mode
bool X86DAGToDAGISel::MatchAddress(SDOperand N, X86ISelAddressMode &AM,
- bool isRoot) {
+ bool isRoot, unsigned Depth) {
+ if (Depth > 5) {
+ // Default, generate it as a register.
+ AM.BaseType = X86ISelAddressMode::RegBase;
+ AM.Base.Reg = N;
+ return false;
+ }
+
// RIP relative addressing: %rip + 32-bit displacement!
if (AM.isRIPRel) {
if (!AM.ES && AM.JT != -1 && N.getOpcode() == ISD::Constant) {
SDOperand N0 = N.getOperand(0);
if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(N0)) {
GlobalValue *GV = G->getGlobal();
- bool isAbs32 = !is64Bit ||
- (isStatic && !(GV->isExternal() || GV->hasWeakLinkage() ||
- GV->hasLinkOnceLinkage()));
+ bool isAbs32 = !is64Bit || isStatic;
if (isAbs32 || isRoot) {
- AM.GV = G->getGlobal();
+ AM.GV = GV;
AM.Disp += G->getOffset();
AM.isRIPRel = !isAbs32;
return false;
if (!Available &&
AM.BaseType == X86ISelAddressMode::RegBase &&
AM.Base.Reg.Val == 0 &&
- AM.IndexReg.Val == 0)
+ AM.IndexReg.Val == 0) {
if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.Val->getOperand(1)))
if (CN->getValue() == 3 || CN->getValue() == 5 || CN->getValue() == 9) {
AM.Scale = unsigned(CN->getValue())-1;
AM.IndexReg = AM.Base.Reg = Reg;
return false;
}
+ }
break;
- case ISD::ADD: {
+ case ISD::ADD:
if (!Available) {
X86ISelAddressMode Backup = AM;
- if (!MatchAddress(N.Val->getOperand(0), AM, false) &&
- !MatchAddress(N.Val->getOperand(1), AM, false))
+ if (!MatchAddress(N.Val->getOperand(0), AM, false, Depth+1) &&
+ !MatchAddress(N.Val->getOperand(1), AM, false, Depth+1))
return false;
AM = Backup;
- if (!MatchAddress(N.Val->getOperand(1), AM, false) &&
- !MatchAddress(N.Val->getOperand(0), AM, false))
+ if (!MatchAddress(N.Val->getOperand(1), AM, false, Depth+1) &&
+ !MatchAddress(N.Val->getOperand(0), AM, false, Depth+1))
return false;
AM = Backup;
}
break;
- }
- case ISD::OR: {
+ case ISD::OR:
+ // Handle "X | C" as "X + C" iff X is known to have C bits clear.
if (!Available) {
- X86ISelAddressMode Backup = AM;
- // Look for (x << c1) | c2 where (c2 < c1)
- ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.Val->getOperand(0));
- if (CN && !MatchAddress(N.Val->getOperand(1), AM, false)) {
- if (AM.GV == NULL && AM.Disp == 0 && CN->getValue() < AM.Scale) {
- AM.Disp = CN->getValue();
+ if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
+ X86ISelAddressMode Backup = AM;
+ // Start with the LHS as an addr mode.
+ if (!MatchAddress(N.getOperand(0), AM, false) &&
+ // Address could not have picked a GV address for the displacement.
+ AM.GV == NULL &&
+ // On x86-64, the resultant disp must fit in 32-bits.
+ isInt32(AM.Disp + CN->getSignExtended()) &&
+ // Check to see if the LHS & C is zero.
+ TLI.MaskedValueIsZero(N.getOperand(0), CN->getValue())) {
+ AM.Disp += CN->getValue();
return false;
}
+ AM = Backup;
}
- AM = Backup;
- CN = dyn_cast<ConstantSDNode>(N.Val->getOperand(1));
- if (CN && !MatchAddress(N.Val->getOperand(0), AM, false)) {
- if (AM.GV == NULL && AM.Disp == 0 && CN->getValue() < AM.Scale) {
- AM.Disp = CN->getValue();
- return false;
- }
- }
- AM = Backup;
}
break;
}
- }
// Is the base register already occupied?
if (AM.BaseType != X86ISelAddressMode::RegBase || AM.Base.Reg.Val) {
else
AM.IndexReg = CurDAG->getRegister(0, VT);
- if (AM.Scale > 2)
- Complexity += 2;
- // Don't match just leal(,%reg,2). It's cheaper to do addl %reg, %reg
- else if (AM.Scale > 1)
+ // Don't match just leal(,%reg,2). It's cheaper to do addl %reg, %reg, or with
+ // a simple shift.
+ if (AM.Scale > 1)
Complexity++;
// FIXME: We are artificially lowering the criteria to turn ADD %reg, $GA
if (AM.GV || AM.CP || AM.ES || AM.JT != -1) {
// For X86-64, we should always use lea to materialize RIP relative
// addresses.
- if (Subtarget->is64Bit() && TM.getRelocationModel() != Reloc::Static)
+ if (Subtarget->is64Bit())
Complexity = 4;
else
Complexity += 2;
MachineBasicBlock &FirstMBB = BB->getParent()->front();
MachineBasicBlock::iterator MBBI = FirstMBB.begin();
SSARegMap *RegMap = BB->getParent()->getSSARegMap();
- GlobalBaseReg = RegMap->createVirtualRegister(X86::GR32RegisterClass);
+ unsigned PC = RegMap->createVirtualRegister(X86::GR32RegisterClass);
+
const TargetInstrInfo *TII = TM.getInstrInfo();
BuildMI(FirstMBB, MBBI, TII->get(X86::MovePCtoStack));
- BuildMI(FirstMBB, MBBI, TII->get(X86::POP32r), GlobalBaseReg);
+ BuildMI(FirstMBB, MBBI, TII->get(X86::POP32r), PC);
+
+ // If we're using vanilla 'GOT' PIC style, we should use relative addressing
+ // not to pc, but to _GLOBAL_ADDRESS_TABLE_ external
+ if (TM.getRelocationModel() == Reloc::PIC_ &&
+ Subtarget->isPICStyleGOT()) {
+ GlobalBaseReg = RegMap->createVirtualRegister(X86::GR32RegisterClass);
+ BuildMI(FirstMBB, MBBI, TII->get(X86::ADD32ri), GlobalBaseReg).
+ addReg(PC).
+ addExternalSymbol("_GLOBAL_OFFSET_TABLE_");
+ } else {
+ GlobalBaseReg = PC;
+ }
+
}
return CurDAG->getRegister(GlobalBaseReg, TLI.getPointerTy()).Val;
}
projects / oota-llvm.git / blobdiff