default:
return TargetLowering::findRepresentativeClass(VT);
case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
- RRC = Subtarget->is64Bit() ?
- (const TargetRegisterClass*)&X86::GR64RegClass :
- (const TargetRegisterClass*)&X86::GR32RegClass;
+ RRC = Subtarget->is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
break;
case MVT::x86mmx:
RRC = &X86::VR64RegClass;
if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
isa<ConstantSDNode>(N2)) {
unsigned Opc;
- if (VT == MVT::v8i16)
+ if (VT == MVT::v8i16) {
Opc = X86ISD::PINSRW;
- else if (VT == MVT::v16i8)
- Opc = X86ISD::PINSRB;
- else
+ } else {
+ assert(VT == MVT::v16i8);
Opc = X86ISD::PINSRB;
+ }
// Transform it so it match pinsr{b,w} which expects a GR32 as its second
// argument.
}
enum IntrinsicType {
- GATHER, SCATTER, PREFETCH, RDSEED, RDRAND, RDPMC, RDTSC, XTEST
+ GATHER, SCATTER, PREFETCH, RDSEED, RDRAND, RDPMC, RDTSC, XTEST, ADX
};
struct IntrinsicData {
IntrinsicData(RDTSC, X86ISD::RDTSCP_DAG, 0)));
IntrMap.insert(std::make_pair(Intrinsic::x86_rdpmc,
IntrinsicData(RDPMC, X86ISD::RDPMC_DAG, 0)));
+ IntrMap.insert(std::make_pair(Intrinsic::x86_addcarryx_u32,
+ IntrinsicData(ADX, X86ISD::ADC, 0)));
+ IntrMap.insert(std::make_pair(Intrinsic::x86_addcarryx_u64,
+ IntrinsicData(ADX, X86ISD::ADC, 0)));
+ IntrMap.insert(std::make_pair(Intrinsic::x86_addcarry_u32,
+ IntrinsicData(ADX, X86ISD::ADC, 0)));
+ IntrMap.insert(std::make_pair(Intrinsic::x86_addcarry_u64,
+ IntrinsicData(ADX, X86ISD::ADC, 0)));
+ IntrMap.insert(std::make_pair(Intrinsic::x86_subborrow_u32,
+ IntrinsicData(ADX, X86ISD::SBB, 0)));
+ IntrMap.insert(std::make_pair(Intrinsic::x86_subborrow_u64,
+ IntrinsicData(ADX, X86ISD::SBB, 0)));
Initialized = true;
}
return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
Ret, SDValue(InTrans.getNode(), 1));
}
+ // ADC/ADCX/SBB
+ case ADX: {
+ SmallVector<SDValue, 2> Results;
+ SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
+ SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0), MVT::Other);
+ SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(2),
+ DAG.getConstant(-1, MVT::i8));
+ SDValue Res = DAG.getNode(Intr.Opc0, dl, VTs, Op.getOperand(3),
+ Op.getOperand(4), GenCF.getValue(1));
+ SDValue Store = DAG.getStore(Op.getOperand(0), dl, Res.getValue(0),
+ Op.getOperand(5), MachinePointerInfo(),
+ false, false, 0);
+ SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
+ DAG.getConstant(X86::COND_B, MVT::i8),
+ Res.getValue(1));
+ Results.push_back(SetCC);
+ Results.push_back(Store);
+ return DAG.getMergeValues(Results, dl);
+ }
}
llvm_unreachable("Unknown Intrinsic Type");
}