//===----------------------------------------------------------------------===//
#include "X86.h"
+#include "X86InstrBuilder.h"
#include "X86ISelLowering.h"
#include "X86TargetMachine.h"
#include "llvm/CallingConv.h"
X86TargetLowering::X86TargetLowering(TargetMachine &TM)
: TargetLowering(TM) {
+ Subtarget = &TM.getSubtarget<X86Subtarget>();
+ X86ScalarSSE = Subtarget->hasSSE2();
+
// Set up the TargetLowering object.
// X86 is weird, it always uses i8 for shift amounts and setcc results.
setShiftAmountType(MVT::i8);
setSetCCResultType(MVT::i8);
setSetCCResultContents(ZeroOrOneSetCCResult);
+ setSchedulingPreference(SchedulingForRegPressure);
setShiftAmountFlavor(Mask); // shl X, 32 == shl X, 0
-
+ setStackPointerRegisterToSaveRestore(X86::ESP);
+
// Set up the register classes.
addRegisterClass(MVT::i8, X86::R8RegisterClass);
addRegisterClass(MVT::i16, X86::R16RegisterClass);
setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
- setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
+
+ if (X86ScalarSSE)
+ // No SSE i64 SINT_TO_FP, so expand i32 UINT_TO_FP instead.
+ setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Expand);
+ else
+ setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
// Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
// this operation.
setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
- if (X86DAGIsel) {
+ if (!X86PatIsel) {
setOperationAction(ISD::BRCOND , MVT::Other, Custom);
}
setOperationAction(ISD::BRCONDTWOWAY , MVT::Other, Expand);
setOperationAction(ISD::CTLZ , MVT::i32 , Expand);
setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
- if (!X86DAGIsel) {
+ if (X86PatIsel) {
+ setOperationAction(ISD::BSWAP , MVT::i32 , Expand);
setOperationAction(ISD::ROTL , MVT::i8 , Expand);
setOperationAction(ISD::ROTR , MVT::i8 , Expand);
setOperationAction(ISD::ROTL , MVT::i16 , Expand);
setOperationAction(ISD::ROTL , MVT::i32 , Expand);
setOperationAction(ISD::ROTR , MVT::i32 , Expand);
}
+ setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
setOperationAction(ISD::READIO , MVT::i1 , Expand);
setOperationAction(ISD::READIO , MVT::i8 , Expand);
// These should be promoted to a larger select which is supported.
setOperationAction(ISD::SELECT , MVT::i1 , Promote);
setOperationAction(ISD::SELECT , MVT::i8 , Promote);
- if (X86DAGIsel) {
+ if (!X86PatIsel) {
// X86 wants to expand cmov itself.
setOperationAction(ISD::SELECT , MVT::i16 , Custom);
setOperationAction(ISD::SELECT , MVT::i32 , Custom);
setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand);
+ // VASTART needs to be custom lowered to use the VarArgsFrameIndex
+ setOperationAction(ISD::VASTART , MVT::Other, Custom);
+
+ // Use the default implementation.
+ setOperationAction(ISD::VAARG , MVT::Other, Expand);
+ setOperationAction(ISD::VACOPY , MVT::Other, Expand);
+ setOperationAction(ISD::VAEND , MVT::Other, Expand);
+ setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
+ setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
+ setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Expand);
+
if (X86ScalarSSE) {
// Set up the FP register classes.
addRegisterClass(MVT::f32, X86::FR32RegisterClass);
setOperationAction(ISD::FNEG , MVT::f32, Expand);
setOperationAction(ISD::FREM , MVT::f32, Expand);
+ // Expand FP immediates into loads from the stack, except for the special
+ // cases we handle.
+ setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
+ setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
addLegalFPImmediate(+0.0); // xorps / xorpd
} else {
// Set up the FP register classes.
addRegisterClass(MVT::f64, X86::RFPRegisterClass);
-
- if (X86DAGIsel) {
+
+ setOperationAction(ISD::UNDEF, MVT::f64, Expand);
+
+ if (!X86PatIsel) {
setOperationAction(ISD::SINT_TO_FP, MVT::i16, Custom);
setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
}
setOperationAction(ISD::FCOS , MVT::f64 , Expand);
}
+ setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
addLegalFPImmediate(+0.0); // FLD0
addLegalFPImmediate(+1.0); // FLD1
addLegalFPImmediate(-0.0); // FLD0/FCHS
return LowerCCCCallTo(Chain, RetTy, isVarArg, isTailCall, Callee, Args, DAG);
}
-SDOperand X86TargetLowering::LowerReturnTo(SDOperand Chain, SDOperand Op,
- SelectionDAG &DAG) {
- if (!X86DAGIsel)
- return DAG.getNode(ISD::RET, MVT::Other, Chain, Op);
-
- SDOperand Copy;
- MVT::ValueType OpVT = Op.getValueType();
- switch (OpVT) {
- default: assert(0 && "Unknown type to return!");
- case MVT::i32:
- Copy = DAG.getCopyToReg(Chain, X86::EAX, Op, SDOperand());
- break;
- case MVT::i64: {
- SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op,
- DAG.getConstant(1, MVT::i32));
- SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op,
- DAG.getConstant(0, MVT::i32));
- Copy = DAG.getCopyToReg(Chain, X86::EDX, Hi, SDOperand());
- Copy = DAG.getCopyToReg(Copy, X86::EAX, Lo, Copy.getValue(1));
- break;
- }
- case MVT::f32:
- case MVT::f64:
- if (!X86ScalarSSE) {
- if (OpVT == MVT::f32)
- Op = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Op);
- std::vector<MVT::ValueType> Tys;
- Tys.push_back(MVT::Other);
- Tys.push_back(MVT::Flag);
- std::vector<SDOperand> Ops;
- Ops.push_back(Chain);
- Ops.push_back(Op);
- Copy = DAG.getNode(X86ISD::FP_SET_RESULT, Tys, Ops);
- } else {
- // Spill the value to memory and reload it into top of stack.
- unsigned Size = MVT::getSizeInBits(OpVT)/8;
- MachineFunction &MF = DAG.getMachineFunction();
- int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size);
- SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
- Chain = DAG.getNode(ISD::STORE, MVT::Other, Chain, Op,
- StackSlot, DAG.getSrcValue(NULL));
- std::vector<MVT::ValueType> Tys;
- Tys.push_back(MVT::f64);
- Tys.push_back(MVT::Other);
- std::vector<SDOperand> Ops;
- Ops.push_back(Chain);
- Ops.push_back(StackSlot);
- Ops.push_back(DAG.getValueType(OpVT));
- Copy = DAG.getNode(X86ISD::FLD, Tys, Ops);
- Tys.clear();
- Tys.push_back(MVT::Other);
- Tys.push_back(MVT::Flag);
- Ops.clear();
- Ops.push_back(Copy.getValue(1));
- Ops.push_back(Copy);
- Copy = DAG.getNode(X86ISD::FP_SET_RESULT, Tys, Ops);
- }
- break;
- }
-
- return DAG.getNode(X86ISD::RET_FLAG, MVT::Other,
- Copy, DAG.getConstant(getBytesToPopOnReturn(), MVT::i16),
- Copy.getValue(1));
-}
-
//===----------------------------------------------------------------------===//
// C Calling Convention implementation
//===----------------------------------------------------------------------===//
break;
}
- if (X86DAGIsel) {
+ if (!X86PatIsel) {
std::vector<MVT::ValueType> NodeTys;
NodeTys.push_back(MVT::Other); // Returns a chain
NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
Chain = DAG.getNode(X86ISD::CALL, NodeTys, Ops);
SDOperand InFlag = Chain.getValue(1);
+ NodeTys.clear();
+ NodeTys.push_back(MVT::Other); // Returns a chain
+ NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
+ Ops.clear();
+ Ops.push_back(Chain);
+ Ops.push_back(DAG.getConstant(NumBytes, getPointerTy()));
+ Ops.push_back(DAG.getConstant(0, getPointerTy()));
+ Ops.push_back(InFlag);
+ Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, Ops);
+ InFlag = Chain.getValue(1);
+
SDOperand RetVal;
if (RetTyVT != MVT::isVoid) {
switch (RetTyVT) {
case MVT::i8:
RetVal = DAG.getCopyFromReg(Chain, X86::AL, MVT::i8, InFlag);
Chain = RetVal.getValue(1);
+ if (RetTyVT == MVT::i1)
+ RetVal = DAG.getNode(ISD::TRUNCATE, MVT::i1, RetVal);
break;
case MVT::i16:
RetVal = DAG.getCopyFromReg(Chain, X86::AX, MVT::i16, InFlag);
std::vector<MVT::ValueType> Tys;
Tys.push_back(MVT::f64);
Tys.push_back(MVT::Other);
+ Tys.push_back(MVT::Flag);
std::vector<SDOperand> Ops;
Ops.push_back(Chain);
Ops.push_back(InFlag);
RetVal = DAG.getNode(X86ISD::FP_GET_RESULT, Tys, Ops);
- Chain = RetVal.getValue(1);
+ Chain = RetVal.getValue(1);
+ InFlag = RetVal.getValue(2);
if (X86ScalarSSE) {
+ // FIXME:Currently the FST is flagged to the FP_GET_RESULT. This
+ // shouldn't be necessary except for RFP cannot be live across
+ // multiple blocks. When stackifier is fixed, they can be uncoupled.
unsigned Size = MVT::getSizeInBits(MVT::f64)/8;
MachineFunction &MF = DAG.getMachineFunction();
int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size);
Ops.push_back(RetVal);
Ops.push_back(StackSlot);
Ops.push_back(DAG.getValueType(RetTyVT));
+ Ops.push_back(InFlag);
Chain = DAG.getNode(X86ISD::FST, Tys, Ops);
RetVal = DAG.getLoad(RetTyVT, Chain, StackSlot,
DAG.getSrcValue(NULL));
Chain = RetVal.getValue(1);
- } else if (RetTyVT == MVT::f32)
+ }
+
+ if (RetTyVT == MVT::f32 && !X86ScalarSSE)
+ // FIXME: we would really like to remember that this FP_ROUND
+ // operation is okay to eliminate if we allow excess FP precision.
RetVal = DAG.getNode(ISD::FP_ROUND, MVT::f32, RetVal);
break;
}
}
}
- Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
- DAG.getConstant(NumBytes, getPointerTy()),
- DAG.getConstant(0, getPointerTy()));
return std::make_pair(RetVal, Chain);
} else {
std::vector<SDOperand> Ops;
}
}
-SDOperand
-X86TargetLowering::LowerVAStart(SDOperand Chain, SDOperand VAListP,
- Value *VAListV, SelectionDAG &DAG) {
- // vastart just stores the address of the VarArgsFrameIndex slot.
- SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32);
- return DAG.getNode(ISD::STORE, MVT::Other, Chain, FR, VAListP,
- DAG.getSrcValue(VAListV));
-}
-
-
-std::pair<SDOperand,SDOperand>
-X86TargetLowering::LowerVAArg(SDOperand Chain, SDOperand VAListP,
- Value *VAListV, const Type *ArgTy,
- SelectionDAG &DAG) {
- MVT::ValueType ArgVT = getValueType(ArgTy);
- SDOperand Val = DAG.getLoad(MVT::i32, Chain,
- VAListP, DAG.getSrcValue(VAListV));
- SDOperand Result = DAG.getLoad(ArgVT, Chain, Val,
- DAG.getSrcValue(NULL));
- unsigned Amt;
- if (ArgVT == MVT::i32)
- Amt = 4;
- else {
- assert((ArgVT == MVT::i64 || ArgVT == MVT::f64) &&
- "Other types should have been promoted for varargs!");
- Amt = 8;
- }
- Val = DAG.getNode(ISD::ADD, Val.getValueType(), Val,
- DAG.getConstant(Amt, Val.getValueType()));
- Chain = DAG.getNode(ISD::STORE, MVT::Other, Chain,
- Val, VAListP, DAG.getSrcValue(VAListV));
- return std::make_pair(Result, Chain);
-}
-
//===----------------------------------------------------------------------===//
// Fast Calling Convention implementation
//===----------------------------------------------------------------------===//
// Arguments go on the stack in reverse order, as specified by the ABI.
unsigned ArgOffset = 0;
- SDOperand StackPtr = DAG.getCopyFromReg(DAG.getEntryNode(),
- X86::ESP, MVT::i32);
+ SDOperand StackPtr = DAG.getRegister(X86::ESP, MVT::i32);
NumIntRegs = 0;
std::vector<SDOperand> Stores;
std::vector<SDOperand> RegValuesToPass;
break;
}
- if (X86DAGIsel) {
+ if (!X86PatIsel) {
// Build a sequence of copy-to-reg nodes chained together with token chain
// and flag operands which copy the outgoing args into registers.
SDOperand InFlag;
Chain = DAG.getNode(X86ISD::CALL, NodeTys, Ops);
InFlag = Chain.getValue(1);
+ NodeTys.clear();
+ NodeTys.push_back(MVT::Other); // Returns a chain
+ NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
+ Ops.clear();
+ Ops.push_back(Chain);
+ Ops.push_back(DAG.getConstant(ArgOffset, getPointerTy()));
+ Ops.push_back(DAG.getConstant(ArgOffset, getPointerTy()));
+ Ops.push_back(InFlag);
+ Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, Ops);
+ InFlag = Chain.getValue(1);
+
SDOperand RetVal;
if (RetTyVT != MVT::isVoid) {
switch (RetTyVT) {
case MVT::i8:
RetVal = DAG.getCopyFromReg(Chain, X86::AL, MVT::i8, InFlag);
Chain = RetVal.getValue(1);
+ if (RetTyVT == MVT::i1)
+ RetVal = DAG.getNode(ISD::TRUNCATE, MVT::i1, RetVal);
break;
case MVT::i16:
RetVal = DAG.getCopyFromReg(Chain, X86::AX, MVT::i16, InFlag);
std::vector<MVT::ValueType> Tys;
Tys.push_back(MVT::f64);
Tys.push_back(MVT::Other);
+ Tys.push_back(MVT::Flag);
std::vector<SDOperand> Ops;
Ops.push_back(Chain);
Ops.push_back(InFlag);
RetVal = DAG.getNode(X86ISD::FP_GET_RESULT, Tys, Ops);
- Chain = RetVal.getValue(1);
+ Chain = RetVal.getValue(1);
+ InFlag = RetVal.getValue(2);
if (X86ScalarSSE) {
+ // FIXME:Currently the FST is flagged to the FP_GET_RESULT. This
+ // shouldn't be necessary except for RFP cannot be live across
+ // multiple blocks. When stackifier is fixed, they can be uncoupled.
unsigned Size = MVT::getSizeInBits(MVT::f64)/8;
MachineFunction &MF = DAG.getMachineFunction();
int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size);
Ops.push_back(RetVal);
Ops.push_back(StackSlot);
Ops.push_back(DAG.getValueType(RetTyVT));
+ Ops.push_back(InFlag);
Chain = DAG.getNode(X86ISD::FST, Tys, Ops);
RetVal = DAG.getLoad(RetTyVT, Chain, StackSlot,
DAG.getSrcValue(NULL));
Chain = RetVal.getValue(1);
- } else if (RetTyVT == MVT::f32)
+ }
+
+ if (RetTyVT == MVT::f32 && !X86ScalarSSE)
+ // FIXME: we would really like to remember that this FP_ROUND
+ // operation is okay to eliminate if we allow excess FP precision.
RetVal = DAG.getNode(ISD::FP_ROUND, MVT::f32, RetVal);
break;
}
}
}
- Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
- DAG.getConstant(ArgOffset, getPointerTy()),
- DAG.getConstant(ArgOffset, getPointerTy()));
return std::make_pair(RetVal, Chain);
} else {
std::vector<SDOperand> Ops;
MachineBasicBlock *
X86TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
MachineBasicBlock *BB) {
- assert((MI->getOpcode() == X86::CMOV_FR32 ||
- MI->getOpcode() == X86::CMOV_FR64) &&
- "Unexpected instr type to insert");
-
- // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
- // control-flow pattern. The incoming instruction knows the destination vreg
- // to set, the condition code register to branch on, the true/false values to
- // select between, and a branch opcode to use.
- const BasicBlock *LLVM_BB = BB->getBasicBlock();
- ilist<MachineBasicBlock>::iterator It = BB;
- ++It;
+ switch (MI->getOpcode()) {
+ default: assert(false && "Unexpected instr type to insert");
+ case X86::CMOV_FR32:
+ case X86::CMOV_FR64: {
+ // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
+ // control-flow pattern. The incoming instruction knows the destination vreg
+ // to set, the condition code register to branch on, the true/false values to
+ // select between, and a branch opcode to use.
+ const BasicBlock *LLVM_BB = BB->getBasicBlock();
+ ilist<MachineBasicBlock>::iterator It = BB;
+ ++It;
- // thisMBB:
- // ...
- // TrueVal = ...
- // cmpTY ccX, r1, r2
- // bCC copy1MBB
- // fallthrough --> copy0MBB
- MachineBasicBlock *thisMBB = BB;
- MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
- MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
- unsigned Opc = getCondBrOpcodeForX86CC(MI->getOperand(3).getImmedValue());
- BuildMI(BB, Opc, 1).addMBB(sinkMBB);
- MachineFunction *F = BB->getParent();
- F->getBasicBlockList().insert(It, copy0MBB);
- F->getBasicBlockList().insert(It, sinkMBB);
- // Update machine-CFG edges
- BB->addSuccessor(copy0MBB);
- BB->addSuccessor(sinkMBB);
+ // thisMBB:
+ // ...
+ // TrueVal = ...
+ // cmpTY ccX, r1, r2
+ // bCC copy1MBB
+ // fallthrough --> copy0MBB
+ MachineBasicBlock *thisMBB = BB;
+ MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
+ MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
+ unsigned Opc = getCondBrOpcodeForX86CC(MI->getOperand(3).getImmedValue());
+ BuildMI(BB, Opc, 1).addMBB(sinkMBB);
+ MachineFunction *F = BB->getParent();
+ F->getBasicBlockList().insert(It, copy0MBB);
+ F->getBasicBlockList().insert(It, sinkMBB);
+ // Update machine-CFG edges
+ BB->addSuccessor(copy0MBB);
+ BB->addSuccessor(sinkMBB);
- // copy0MBB:
- // %FalseValue = ...
- // # fallthrough to sinkMBB
- BB = copy0MBB;
+ // copy0MBB:
+ // %FalseValue = ...
+ // # fallthrough to sinkMBB
+ BB = copy0MBB;
- // Update machine-CFG edges
- BB->addSuccessor(sinkMBB);
+ // Update machine-CFG edges
+ BB->addSuccessor(sinkMBB);
- // sinkMBB:
- // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
- // ...
- BB = sinkMBB;
- BuildMI(BB, X86::PHI, 4, MI->getOperand(0).getReg())
- .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
- .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
-
- delete MI; // The pseudo instruction is gone now.
- return BB;
+ // sinkMBB:
+ // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
+ // ...
+ BB = sinkMBB;
+ BuildMI(BB, X86::PHI, 4, MI->getOperand(0).getReg())
+ .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
+ .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
+
+ delete MI; // The pseudo instruction is gone now.
+ return BB;
+ }
+
+ case X86::FP_TO_INT16_IN_MEM:
+ case X86::FP_TO_INT32_IN_MEM:
+ case X86::FP_TO_INT64_IN_MEM: {
+ // Change the floating point control register to use "round towards zero"
+ // mode when truncating to an integer value.
+ MachineFunction *F = BB->getParent();
+ int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2);
+ addFrameReference(BuildMI(BB, X86::FNSTCW16m, 4), CWFrameIdx);
+
+ // Load the old value of the high byte of the control word...
+ unsigned OldCW =
+ F->getSSARegMap()->createVirtualRegister(X86::R16RegisterClass);
+ addFrameReference(BuildMI(BB, X86::MOV16rm, 4, OldCW), CWFrameIdx);
+
+ // Set the high part to be round to zero...
+ addFrameReference(BuildMI(BB, X86::MOV16mi, 5), CWFrameIdx).addImm(0xC7F);
+
+ // Reload the modified control word now...
+ addFrameReference(BuildMI(BB, X86::FLDCW16m, 4), CWFrameIdx);
+
+ // Restore the memory image of control word to original value
+ addFrameReference(BuildMI(BB, X86::MOV16mr, 5), CWFrameIdx).addReg(OldCW);
+
+ // Get the X86 opcode to use.
+ unsigned Opc;
+ switch (MI->getOpcode()) {
+ default: assert(0 && "illegal opcode!");
+ case X86::FP_TO_INT16_IN_MEM: Opc = X86::FpIST16m; break;
+ case X86::FP_TO_INT32_IN_MEM: Opc = X86::FpIST32m; break;
+ case X86::FP_TO_INT64_IN_MEM: Opc = X86::FpIST64m; break;
+ }
+
+ X86AddressMode AM;
+ MachineOperand &Op = MI->getOperand(0);
+ if (Op.isRegister()) {
+ AM.BaseType = X86AddressMode::RegBase;
+ AM.Base.Reg = Op.getReg();
+ } else {
+ AM.BaseType = X86AddressMode::FrameIndexBase;
+ AM.Base.FrameIndex = Op.getFrameIndex();
+ }
+ Op = MI->getOperand(1);
+ if (Op.isImmediate())
+ AM.Scale = Op.getImmedValue();
+ Op = MI->getOperand(2);
+ if (Op.isImmediate())
+ AM.IndexReg = Op.getImmedValue();
+ Op = MI->getOperand(3);
+ if (Op.isGlobalAddress()) {
+ AM.GV = Op.getGlobal();
+ } else {
+ AM.Disp = Op.getImmedValue();
+ }
+ addFullAddress(BuildMI(BB, Opc, 5), AM).addReg(MI->getOperand(4).getReg());
+
+ // Reload the original control word now.
+ addFrameReference(BuildMI(BB, X86::FLDCW16m, 4), CWFrameIdx);
+
+ delete MI; // The pseudo instruction is gone now.
+ return BB;
+ }
+ }
}
SDOperand ShOpHi = Op.getOperand(1);
SDOperand ShAmt = Op.getOperand(2);
SDOperand Tmp1 = isSRA ? DAG.getNode(ISD::SRA, MVT::i32, ShOpHi,
- DAG.getConstant(31, MVT::i32))
+ DAG.getConstant(31, MVT::i8))
: DAG.getConstant(0, MVT::i32);
SDOperand Tmp2, Tmp3;
Tmp3 = DAG.getNode(ISD::SHL, MVT::i32, ShOpLo, ShAmt);
} else {
Tmp2 = DAG.getNode(X86ISD::SHRD, MVT::i32, ShOpLo, ShOpHi, ShAmt);
- Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SHL, MVT::i32, ShOpHi, ShAmt);
+ Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, MVT::i32, ShOpHi, ShAmt);
}
SDOperand InFlag = DAG.getNode(X86ISD::TEST, MVT::Flag,
case ISD::SELECT: {
MVT::ValueType VT = Op.getValueType();
bool isFP = MVT::isFloatingPoint(VT);
- bool isFPStack = isFP && (X86Vector < SSE2);
- bool isFPSSE = isFP && (X86Vector >= SSE2);
+ bool isFPStack = isFP && !X86ScalarSSE;
+ bool isFPSSE = isFP && X86ScalarSSE;
bool addTest = false;
SDOperand Op0 = Op.getOperand(0);
SDOperand Cond, CC;
// If the X86ISD::SETCC has more than one use, then it's probably better
// to use a test instead of duplicating the X86ISD::CMP (for register
// pressure reason).
- if (Cond.hasOneUse() && Cond.getOperand(1).getOpcode() == X86ISD::CMP) {
+ if (Op0.getOperand(1).getOpcode() == X86ISD::CMP) {
+ if (!Op0.hasOneUse()) {
+ std::vector<MVT::ValueType> Tys;
+ for (unsigned i = 0; i < Op0.Val->getNumValues(); ++i)
+ Tys.push_back(Op0.Val->getValueType(i));
+ std::vector<SDOperand> Ops;
+ for (unsigned i = 0; i < Op0.getNumOperands(); ++i)
+ Ops.push_back(Op0.getOperand(i));
+ Op0 = DAG.getNode(X86ISD::SETCC, Tys, Ops);
+ }
+
CC = Op0.getOperand(0);
Cond = Op0.getOperand(1);
+ // Make a copy as flag result cannot be used by more than one.
+ Cond = DAG.getNode(X86ISD::CMP, MVT::Flag,
+ Cond.getOperand(0), Cond.getOperand(1));
addTest =
- !(isFPStack &&
- !hasFPCMov(cast<ConstantSDNode>(CC)->getSignExtended()));
+ isFPStack && !hasFPCMov(cast<ConstantSDNode>(CC)->getSignExtended());
} else
addTest = true;
} else if (Op0.getOpcode() == ISD::SETCC) {
CC = DAG.getConstant(X86CC, MVT::i8);
Cond = DAG.getNode(X86ISD::CMP, MVT::Flag,
Op0.getOperand(0), Op0.getOperand(1));
- addTest = true;
} else
addTest = true;
- if (!addTest) {
- CC = DAG.getConstant(X86ISD::COND_E, MVT::i8);
+ if (addTest) {
+ CC = DAG.getConstant(X86ISD::COND_NE, MVT::i8);
Cond = DAG.getNode(X86ISD::TEST, MVT::Flag, Op0, Op0);
}
Tys.push_back(Op.getValueType());
Tys.push_back(MVT::Flag);
std::vector<SDOperand> Ops;
- Ops.push_back(Op.getOperand(1));
+ // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
+ // condition is true.
Ops.push_back(Op.getOperand(2));
+ Ops.push_back(Op.getOperand(1));
Ops.push_back(CC);
Ops.push_back(Cond);
return DAG.getNode(X86ISD::CMOV, Tys, Ops);
// If the X86ISD::SETCC has more than one use, then it's probably better
// to use a test instead of duplicating the X86ISD::CMP (for register
// pressure reason).
- if (Cond.hasOneUse() && Cond.getOperand(1).getOpcode() == X86ISD::CMP) {
+ if (Cond.getOperand(1).getOpcode() == X86ISD::CMP) {
+ if (!Cond.hasOneUse()) {
+ std::vector<MVT::ValueType> Tys;
+ for (unsigned i = 0; i < Cond.Val->getNumValues(); ++i)
+ Tys.push_back(Cond.Val->getValueType(i));
+ std::vector<SDOperand> Ops;
+ for (unsigned i = 0; i < Cond.getNumOperands(); ++i)
+ Ops.push_back(Cond.getOperand(i));
+ Cond = DAG.getNode(X86ISD::SETCC, Tys, Ops);
+ }
+
CC = Cond.getOperand(0);
+ Cond = Cond.getOperand(1);
+ // Make a copy as flag result cannot be used by more than one.
Cond = DAG.getNode(X86ISD::CMP, MVT::Flag,
- Cond.getOperand(1).getOperand(0),
- Cond.getOperand(1).getOperand(1));
+ Cond.getOperand(0), Cond.getOperand(1));
} else
addTest = true;
} else if (Cond.getOpcode() == ISD::SETCC) {
return DAG.getNode(X86ISD::BRCOND, Op.getValueType(),
Op.getOperand(0), Op.getOperand(2), CC, Cond);
}
- case ISD::RET: {
- // Can only be return void.
- return DAG.getNode(X86ISD::RET_FLAG, MVT::Other, Op.getOperand(0),
- DAG.getConstant(getBytesToPopOnReturn(), MVT::i16));
- }
case ISD::MEMSET: {
SDOperand InFlag;
SDOperand Chain = Op.getOperand(0);
DAG.getSrcValue(NULL));
return Result;
}
+ case ISD::VASTART: {
+ // vastart just stores the address of the VarArgsFrameIndex slot into the
+ // memory location argument.
+ // FIXME: Replace MVT::i32 with PointerTy
+ SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32);
+ return DAG.getNode(ISD::STORE, MVT::Other, Op.getOperand(0), FR,
+ Op.getOperand(1), Op.getOperand(2));
+ }
+ case ISD::RET: {
+ SDOperand Copy;
+
+ switch(Op.getNumOperands()) {
+ default:
+ assert(0 && "Do not know how to return this many arguments!");
+ abort();
+ case 1:
+ return DAG.getNode(X86ISD::RET_FLAG, MVT::Other, Op.getOperand(0),
+ DAG.getConstant(getBytesToPopOnReturn(), MVT::i16));
+ case 2: {
+ MVT::ValueType ArgVT = Op.getOperand(1).getValueType();
+ if (MVT::isInteger(ArgVT))
+ Copy = DAG.getCopyToReg(Op.getOperand(0), X86::EAX, Op.getOperand(1),
+ SDOperand());
+ else if (!X86ScalarSSE) {
+ std::vector<MVT::ValueType> Tys;
+ Tys.push_back(MVT::Other);
+ Tys.push_back(MVT::Flag);
+ std::vector<SDOperand> Ops;
+ Ops.push_back(Op.getOperand(0));
+ Ops.push_back(Op.getOperand(1));
+ Copy = DAG.getNode(X86ISD::FP_SET_RESULT, Tys, Ops);
+ } else {
+ // Spill the value to memory and reload it into top of stack.
+ unsigned Size = MVT::getSizeInBits(ArgVT)/8;
+ MachineFunction &MF = DAG.getMachineFunction();
+ int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size);
+ SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
+ SDOperand Chain = DAG.getNode(ISD::STORE, MVT::Other, Op.getOperand(0),
+ Op.getOperand(1), StackSlot,
+ DAG.getSrcValue(0));
+ std::vector<MVT::ValueType> Tys;
+ Tys.push_back(MVT::f64);
+ Tys.push_back(MVT::Other);
+ std::vector<SDOperand> Ops;
+ Ops.push_back(Chain);
+ Ops.push_back(StackSlot);
+ Ops.push_back(DAG.getValueType(ArgVT));
+ Copy = DAG.getNode(X86ISD::FLD, Tys, Ops);
+ Tys.clear();
+ Tys.push_back(MVT::Other);
+ Tys.push_back(MVT::Flag);
+ Ops.clear();
+ Ops.push_back(Copy.getValue(1));
+ Ops.push_back(Copy);
+ Copy = DAG.getNode(X86ISD::FP_SET_RESULT, Tys, Ops);
+ }
+ break;
+ }
+ case 3:
+ Copy = DAG.getCopyToReg(Op.getOperand(0), X86::EDX, Op.getOperand(2),
+ SDOperand());
+ Copy = DAG.getCopyToReg(Copy, X86::EAX,Op.getOperand(1),Copy.getValue(1));
+ break;
+ }
+ return DAG.getNode(X86ISD::RET_FLAG, MVT::Other,
+ Copy, DAG.getConstant(getBytesToPopOnReturn(), MVT::i16),
+ Copy.getValue(1));
+ }
}
}
projects / oota-llvm.git / blobdiff