PIC related bug fixes.

[oota-llvm.git] / lib / Target / X86 / X86ISelLowering.cpp

diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index bbf590b8ac3aaf55cc014989bb265630d849aa65..b7a315a8ad8fddbfd089863df11955d07d0a5cb3 100644 (file)
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -236,6 +236,44 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM)
     addLegalFPImmediate(-0.0); // FLD0/FCHS
     addLegalFPImmediate(-1.0); // FLD1/FCHS
   }
+
+  if (TM.getSubtarget<X86Subtarget>().hasMMX()) {
+    addRegisterClass(MVT::v8i8,  X86::VR64RegisterClass);
+    addRegisterClass(MVT::v4i16, X86::VR64RegisterClass);
+    addRegisterClass(MVT::v2i32, X86::VR64RegisterClass);
+
+    // FIXME: We don't support any ConstantVec's yet.  We should custom expand
+    // the ones we do!
+    setOperationAction(ISD::ConstantVec, MVT::v8i8,  Expand);
+    setOperationAction(ISD::ConstantVec, MVT::v4i16, Expand);
+    setOperationAction(ISD::ConstantVec, MVT::v2i32, Expand);
+  }
+
+  if (TM.getSubtarget<X86Subtarget>().hasSSE1()) {
+    addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
+
+    // FIXME: We don't support any ConstantVec's yet.  We should custom expand
+    // the ones we do!
+    setOperationAction(ISD::ConstantVec, MVT::v4f32, Expand);
+  }
+
+  if (TM.getSubtarget<X86Subtarget>().hasSSE2()) {
+    addRegisterClass(MVT::v2f64, X86::VR128RegisterClass);
+    addRegisterClass(MVT::v16i8, X86::VR128RegisterClass);
+    addRegisterClass(MVT::v8i16, X86::VR128RegisterClass);
+    addRegisterClass(MVT::v4i32, X86::VR128RegisterClass);
+    addRegisterClass(MVT::v2i64, X86::VR128RegisterClass);
+
+
+    // FIXME: We don't support any ConstantVec's yet.  We should custom expand
+    // the ones we do!
+    setOperationAction(ISD::ConstantVec, MVT::v2f64, Expand);
+    setOperationAction(ISD::ConstantVec, MVT::v16i8, Expand);
+    setOperationAction(ISD::ConstantVec, MVT::v8i16, Expand);
+    setOperationAction(ISD::ConstantVec, MVT::v4i32, Expand);
+    setOperationAction(ISD::ConstantVec, MVT::v2i64, Expand);
+  }
+
   computeRegisterProperties();
 
   // FIXME: These should be based on subtarget info. Plus, the values should
@@ -1795,10 +1833,9 @@ SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
     SDOperand Result =
       DAG.getTargetConstantPool(CP->get(), getPointerTy(), CP->getAlignment());
     // Only lower ConstantPool on Darwin.
-    if (getTargetMachine().
-        getSubtarget<X86Subtarget>().isTargetDarwin()) {
+    if (getTargetMachine().getSubtarget<X86Subtarget>().isTargetDarwin()) {
       // With PIC, the address is actually $g + Offset.
-      if (PICEnabled)
+      if (getTargetMachine().getRelocationModel() == Reloc::PIC)
         Result = DAG.getNode(ISD::ADD, getPointerTy(),
                 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()), Result);    
     }
@@ -1811,20 +1848,22 @@ SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
     if (getTargetMachine().
         getSubtarget<X86Subtarget>().isTargetDarwin()) {
       GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
-      SDOperand Addr = DAG.getTargetGlobalAddress(GV, getPointerTy());
+      Result = DAG.getNode(X86ISD::TGAWrapper, getPointerTy(),
+                           DAG.getTargetGlobalAddress(GV, getPointerTy()));
       // With PIC, the address is actually $g + Offset.
-      if (PICEnabled)
-        Addr = DAG.getNode(ISD::ADD, getPointerTy(),
-                      DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()), Addr);
+      if (getTargetMachine().getRelocationModel() == Reloc::PIC)
+        Result = DAG.getNode(ISD::ADD, getPointerTy(),
+                    DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()), Result);
 
       // For Darwin, external and weak symbols are indirect, so we want to load
       // the value at address GV, not the value of GV itself.  This means that
       // the GlobalAddress must be in the base or index register of the address,
       // not the GV offset field.
-      if (GV->hasWeakLinkage() || GV->hasLinkOnceLinkage() ||
-          (GV->isExternal() && !GV->hasNotBeenReadFromBytecode()))
+      if (getTargetMachine().getRelocationModel() != Reloc::Static &&
+          (GV->hasWeakLinkage() || GV->hasLinkOnceLinkage() ||
+           (GV->isExternal() && !GV->hasNotBeenReadFromBytecode())))
         Result = DAG.getLoad(MVT::i32, DAG.getEntryNode(),
-                             Addr, DAG.getSrcValue(NULL));
+                             Result, DAG.getSrcValue(NULL));
     }
 
     return Result;
@@ -1938,6 +1977,7 @@ const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
   case X86ISD::REP_MOVS:           return "X86ISD::RET_MOVS";
   case X86ISD::LOAD_PACK:          return "X86ISD::LOAD_PACK";
   case X86ISD::GlobalBaseReg:      return "X86ISD::GlobalBaseReg";
+  case X86ISD::TGAWrapper:         return "X86ISD::TGAWrapper";
   }
 }
 
@@ -1961,8 +2001,8 @@ void X86TargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
 }
 
 std::vector<unsigned> X86TargetLowering::
-getRegForInlineAsmConstraint(const std::string &Constraint,
-                             MVT::ValueType VT) const {
+getRegClassForInlineAsmConstraint(const std::string &Constraint,
+                                  MVT::ValueType VT) const {
   if (Constraint.size() == 1) {
     // FIXME: not handling fp-stack yet!
     // FIXME: not handling MMX registers yet ('y' constraint).
@@ -1993,6 +2033,5 @@ getRegForInlineAsmConstraint(const std::string &Constraint,
     }
   }
   
-  // Handle explicit register names.
-  return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
+  return std::vector<unsigned>();
 }