[asan-assembly-instrumentation] Prologue and epilogue are moved out from InstrumentMe...

[oota-llvm.git] / lib / Target / X86 / X86ISelLowering.cpp

diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index f52e498e5622e47f0e8509a86c42fed9e2247c45..ed846569210241686dd00bd5162e7b7334d7fe1f 100644 (file)
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -2326,6 +2326,7 @@ X86TargetLowering::LowerMemArgument(SDValue Chain,
   }
 }
 
+// FIXME: Get this from tablegen.
 static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
                                                 const X86Subtarget *Subtarget) {
   assert(Subtarget->is64Bit());
@@ -2334,15 +2335,16 @@ static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
     static const MCPhysReg GPR64ArgRegsWin64[] = {
       X86::RCX, X86::RDX, X86::R8,  X86::R9
     };
-    return GPR64ArgRegsWin64;
+    return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
   }
 
   static const MCPhysReg GPR64ArgRegs64Bit[] = {
     X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
   };
-  return GPR64ArgRegs64Bit;
+  return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
 }
 
+// FIXME: Get this from tablegen.
 static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
                                                 CallingConv::ID CallConv,
                                                 const X86Subtarget *Subtarget) {
@@ -2351,6 +2353,7 @@ static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
     // The XMM registers which might contain var arg parameters are shadowed
     // in their paired GPR.  So we only need to save the GPR to their home
     // slots.
+    // TODO: __vectorcall will change this.
     return None;
   }
 
@@ -2369,7 +2372,7 @@ static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
     X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
     X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
   };
-  return XMMArgRegs64Bit;
+  return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
 }
 
 SDValue
@@ -2613,13 +2616,12 @@ X86TargetLowering::LowerFormalArguments(SDValue Chain,
       if (!MemOps.empty())
         Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
     } else {
-      // TODO: Save virtual registers away some where so we can do
-      // getCopyFromReg in the musttail call lowering bb.
+      // Add all GPRs, al, and XMMs to the list of forwards.  We will add then
+      // to the liveout set on a musttail call.
       assert(MFI->hasMustTailInVarArgFunc());
       auto &Forwards = FuncInfo->getForwardedMustTailRegParms();
       typedef X86MachineFunctionInfo::Forward Forward;
 
-      // Add all GPRs, al, and XMMs to the list of forwards.
       for (unsigned I = 0, E = LiveGPRs.size(); I != E; ++I) {
         unsigned VReg =
             MF.getRegInfo().createVirtualRegister(&X86::GR64RegClass);