merge the common darwin settings from the X86/PPC/ARM targets

[oota-llvm.git] / lib / Target / X86 / X86ISelLowering.h

diff --git a/lib/Target/X86/X86ISelLowering.h b/lib/Target/X86/X86ISelLowering.h
index 78d95c0cdd14f5a4c76c245735cd3405eacbfadb..fb4eb6815b2189f57196f3d9cf865c8baf93ae46 100644 (file)
--- a/lib/Target/X86/X86ISelLowering.h
+++ b/lib/Target/X86/X86ISelLowering.h
@@ -243,14 +243,6 @@ namespace llvm {
       ADD, SUB, SMUL, UMUL,
       INC, DEC,
 
-      // ADDC, SUBC - Arithmetic operations setting carry bit.  The normal
-      // arithmetic operations do this, but they represent it as Flag, and
-      // we want the i32 EFLAGS register here.
-      ADDC, SUBC,
-
-      // ADDE, SUBE - Arithmetic operations with extra FLAGS (EFLAGS) inputs.
-      ADDE, SUBE,
-
       // MUL_IMM - X86 specific multiply by immediate.
       MUL_IMM
     };
@@ -386,7 +378,8 @@ namespace llvm {
     /// determining it.
     virtual
     MVT getOptimalMemOpType(uint64_t Size, unsigned Align,
-                            bool isSrcConst, bool isSrcStr) const;
+                            bool isSrcConst, bool isSrcStr,
+                            SelectionDAG &DAG) const;
     
     /// LowerOperation - Provide custom lowering hooks for some operations.
     ///
@@ -584,9 +577,7 @@ namespace llvm {
 
     std::pair<SDValue,SDValue> FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
                                                bool isSigned);
-
-    SDValue LowerADDSUBC(SDValue Op, SelectionDAG &DAG);
-    SDValue LowerADDSUBE(SDValue Op, SelectionDAG &DAG);
+    
     SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG);
     SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG);
     SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG);