//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This file defines a pattern matching instruction selector for X86.
#include "X86.h"
#include "X86InstrBuilder.h"
#include "X86RegisterInfo.h"
-#include "llvm/Constants.h" // FIXME: REMOVE
+#include "X86Subtarget.h"
+#include "llvm/CallingConv.h"
+#include "llvm/Constants.h"
+#include "llvm/Instructions.h"
#include "llvm/Function.h"
-#include "llvm/CodeGen/MachineConstantPool.h" // FIXME: REMOVE
+#include "llvm/CodeGen/MachineConstantPool.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/SSARegMap.h"
#include "llvm/Target/TargetData.h"
#include "llvm/Target/TargetLowering.h"
+#include "llvm/Target/TargetMachine.h"
+#include "llvm/Target/TargetOptions.h"
+#include "llvm/Support/CFG.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/ADT/Statistic.h"
#include <set>
#include <algorithm>
using namespace llvm;
+// FIXME: temporary.
+#include "llvm/Support/CommandLine.h"
+static cl::opt<bool> EnableFastCC("enable-x86-fastcc", cl::Hidden,
+ cl::desc("Enable fastcc on X86"));
+
+namespace {
+ // X86 Specific DAG Nodes
+ namespace X86ISD {
+ enum NodeType {
+ // Start the numbering where the builtin ops leave off.
+ FIRST_NUMBER = ISD::BUILTIN_OP_END,
+
+ /// FILD64m - This instruction implements SINT_TO_FP with a
+ /// 64-bit source in memory and a FP reg result. This corresponds to
+ /// the X86::FILD64m instruction. It has two inputs (token chain and
+ /// address) and two outputs (FP value and token chain).
+ FILD64m,
+
+ /// FP_TO_INT*_IN_MEM - This instruction implements FP_TO_SINT with the
+ /// integer destination in memory and a FP reg source. This corresponds
+ /// to the X86::FIST*m instructions and the rounding mode change stuff. It
+ /// has two inputs (token chain and address) and two outputs (FP value and
+ /// token chain).
+ FP_TO_INT16_IN_MEM,
+ FP_TO_INT32_IN_MEM,
+ FP_TO_INT64_IN_MEM,
+
+ /// CALL/TAILCALL - These operations represent an abstract X86 call
+ /// instruction, which includes a bunch of information. In particular the
+ /// operands of these node are:
+ ///
+ /// #0 - The incoming token chain
+ /// #1 - The callee
+ /// #2 - The number of arg bytes the caller pushes on the stack.
+ /// #3 - The number of arg bytes the callee pops off the stack.
+ /// #4 - The value to pass in AL/AX/EAX (optional)
+ /// #5 - The value to pass in DL/DX/EDX (optional)
+ ///
+ /// The result values of these nodes are:
+ ///
+ /// #0 - The outgoing token chain
+ /// #1 - The first register result value (optional)
+ /// #2 - The second register result value (optional)
+ ///
+ /// The CALL vs TAILCALL distinction boils down to whether the callee is
+ /// known not to modify the caller's stack frame, as is standard with
+ /// LLVM.
+ CALL,
+ TAILCALL,
+ };
+ }
+}
+
//===----------------------------------------------------------------------===//
// X86TargetLowering - X86 Implementation of the TargetLowering interface
namespace {
class X86TargetLowering : public TargetLowering {
int VarArgsFrameIndex; // FrameIndex for start of varargs area.
int ReturnAddrIndex; // FrameIndex for return slot.
+ int BytesToPopOnReturn; // Number of arg bytes ret should pop.
+ int BytesCallerReserves; // Number of arg bytes caller makes.
public:
X86TargetLowering(TargetMachine &TM) : TargetLowering(TM) {
// Set up the TargetLowering object.
- // X86 is wierd, it always uses i8 for shift amounts and setcc results.
+ // X86 is weird, it always uses i8 for shift amounts and setcc results.
setShiftAmountType(MVT::i8);
setSetCCResultType(MVT::i8);
+ setSetCCResultContents(ZeroOrOneSetCCResult);
setShiftAmountFlavor(Mask); // shl X, 32 == shl X, 0
// Set up the register classes.
+ // FIXME: Eliminate these two classes when legalize can handle promotions
+ // well.
+ addRegisterClass(MVT::i1, X86::R8RegisterClass);
addRegisterClass(MVT::i8, X86::R8RegisterClass);
addRegisterClass(MVT::i16, X86::R16RegisterClass);
addRegisterClass(MVT::i32, X86::R32RegisterClass);
- addRegisterClass(MVT::f64, X86::RFPRegisterClass);
-
- // FIXME: Eliminate these two classes when legalize can handle promotions
- // well.
-/**/ addRegisterClass(MVT::i1, X86::R8RegisterClass);
+ // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
+ // operation.
+ setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
+ setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
+ setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
+ setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
+
+ // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
+ // this operation.
+ setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
+ setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
+
+ if (!X86ScalarSSE) {
+ // We can handle SINT_TO_FP and FP_TO_SINT from/TO i64 even though i64
+ // isn't legal.
+ setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
+ setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
+ setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
+ setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
+ }
+
+ // Handle FP_TO_UINT by promoting the destination to a larger signed
+ // conversion.
+ setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
+ setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
+ setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
+
+ if (!X86ScalarSSE)
+ setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
+
+ // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
+ // this operation.
+ setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
+ setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
+ setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
+
+ setOperationAction(ISD::BRCONDTWOWAY , MVT::Other, Expand);
+ setOperationAction(ISD::BRTWOWAY_CC , MVT::Other, Expand);
setOperationAction(ISD::MEMMOVE , MVT::Other, Expand);
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Expand);
- setOperationAction(ISD::ZERO_EXTEND_INREG, MVT::i16 , Expand);
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
- setOperationAction(ISD::ZERO_EXTEND_INREG, MVT::i1 , Expand);
setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
setOperationAction(ISD::SEXTLOAD , MVT::i1 , Expand);
- setOperationAction(ISD::SREM , MVT::f64 , Expand);
-
+ setOperationAction(ISD::FREM , MVT::f64 , Expand);
+ setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
+ setOperationAction(ISD::CTTZ , MVT::i8 , Expand);
+ setOperationAction(ISD::CTLZ , MVT::i8 , Expand);
+ setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
+ setOperationAction(ISD::CTTZ , MVT::i16 , Expand);
+ setOperationAction(ISD::CTLZ , MVT::i16 , Expand);
+ setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
+ setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
+ setOperationAction(ISD::CTLZ , MVT::i32 , Expand);
+
+ setOperationAction(ISD::READIO , MVT::i1 , Expand);
+ setOperationAction(ISD::READIO , MVT::i8 , Expand);
+ setOperationAction(ISD::READIO , MVT::i16 , Expand);
+ setOperationAction(ISD::READIO , MVT::i32 , Expand);
+ setOperationAction(ISD::WRITEIO , MVT::i1 , Expand);
+ setOperationAction(ISD::WRITEIO , MVT::i8 , Expand);
+ setOperationAction(ISD::WRITEIO , MVT::i16 , Expand);
+ setOperationAction(ISD::WRITEIO , MVT::i32 , Expand);
+
// These should be promoted to a larger select which is supported.
-/**/ setOperationAction(ISD::SELECT , MVT::i1 , Promote);
+ setOperationAction(ISD::SELECT , MVT::i1 , Promote);
setOperationAction(ISD::SELECT , MVT::i8 , Promote);
-
+
+ if (X86ScalarSSE) {
+ // Set up the FP register classes.
+ addRegisterClass(MVT::f32, X86::RXMMRegisterClass);
+ addRegisterClass(MVT::f64, X86::RXMMRegisterClass);
+
+ // SSE has no load+extend ops
+ setOperationAction(ISD::EXTLOAD, MVT::f32, Expand);
+ setOperationAction(ISD::ZEXTLOAD, MVT::f32, Expand);
+
+ // SSE has no i16 to fp conversion, only i32
+ setOperationAction(ISD::SINT_TO_FP, MVT::i16, Promote);
+ setOperationAction(ISD::FP_TO_SINT, MVT::i16, Promote);
+
+ // Expand FP_TO_UINT into a select.
+ // FIXME: We would like to use a Custom expander here eventually to do
+ // the optimal thing for SSE vs. the default expansion in the legalizer.
+ setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
+
+ // We don't support sin/cos/sqrt/fmod
+ setOperationAction(ISD::FSIN , MVT::f64, Expand);
+ setOperationAction(ISD::FCOS , MVT::f64, Expand);
+ setOperationAction(ISD::FABS , MVT::f64, Expand);
+ setOperationAction(ISD::FNEG , MVT::f64, Expand);
+ setOperationAction(ISD::FREM , MVT::f64, Expand);
+ setOperationAction(ISD::FSIN , MVT::f32, Expand);
+ setOperationAction(ISD::FCOS , MVT::f32, Expand);
+ setOperationAction(ISD::FABS , MVT::f32, Expand);
+ setOperationAction(ISD::FNEG , MVT::f32, Expand);
+ setOperationAction(ISD::FREM , MVT::f32, Expand);
+
+ addLegalFPImmediate(+0.0); // xorps / xorpd
+ } else {
+ // Set up the FP register classes.
+ addRegisterClass(MVT::f64, X86::RFPRegisterClass);
+
+ if (!UnsafeFPMath) {
+ setOperationAction(ISD::FSIN , MVT::f64 , Expand);
+ setOperationAction(ISD::FCOS , MVT::f64 , Expand);
+ }
+
+ addLegalFPImmediate(+0.0); // FLD0
+ addLegalFPImmediate(+1.0); // FLD1
+ addLegalFPImmediate(-0.0); // FLD0/FCHS
+ addLegalFPImmediate(-1.0); // FLD1/FCHS
+ }
computeRegisterProperties();
-
- addLegalFPImmediate(+0.0); // FLD0
- addLegalFPImmediate(+1.0); // FLD1
- addLegalFPImmediate(-0.0); // FLD0/FCHS
- addLegalFPImmediate(-1.0); // FLD1/FCHS
+
+ maxStoresPerMemSet = 8; // For %llvm.memset -> sequence of stores
+ maxStoresPerMemCpy = 8; // For %llvm.memcpy -> sequence of stores
+ maxStoresPerMemMove = 8; // For %llvm.memmove -> sequence of stores
+ allowUnalignedMemoryAccesses = true; // x86 supports it!
}
+ // Return the number of bytes that a function should pop when it returns (in
+ // addition to the space used by the return address).
+ //
+ unsigned getBytesToPopOnReturn() const { return BytesToPopOnReturn; }
+
+ // Return the number of bytes that the caller reserves for arguments passed
+ // to this function.
+ unsigned getBytesCallerReserves() const { return BytesCallerReserves; }
+
+ /// LowerOperation - Provide custom lowering hooks for some operations.
+ ///
+ virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
+
/// LowerArguments - This hook must be implemented to indicate how we should
/// lower the arguments for the specified function, into the specified DAG.
virtual std::vector<SDOperand>
/// LowerCallTo - This hook lowers an abstract call to a function into an
/// actual call.
virtual std::pair<SDOperand, SDOperand>
- LowerCallTo(SDOperand Chain, const Type *RetTy, SDOperand Callee,
- ArgListTy &Args, SelectionDAG &DAG);
-
- virtual std::pair<SDOperand, SDOperand>
- LowerVAStart(SDOperand Chain, SelectionDAG &DAG);
+ LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg, unsigned CC,
+ bool isTailCall, SDOperand Callee, ArgListTy &Args,
+ SelectionDAG &DAG);
+ virtual SDOperand LowerVAStart(SDOperand Chain, SDOperand VAListP,
+ Value *VAListV, SelectionDAG &DAG);
virtual std::pair<SDOperand,SDOperand>
- LowerVAArgNext(bool isVANext, SDOperand Chain, SDOperand VAList,
- const Type *ArgTy, SelectionDAG &DAG);
+ LowerVAArg(SDOperand Chain, SDOperand VAListP, Value *VAListV,
+ const Type *ArgTy, SelectionDAG &DAG);
virtual std::pair<SDOperand, SDOperand>
LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth,
SelectionDAG &DAG);
+
+ SDOperand getReturnAddressFrameIndex(SelectionDAG &DAG);
+
+ private:
+ // C Calling Convention implementation.
+ std::vector<SDOperand> LowerCCCArguments(Function &F, SelectionDAG &DAG);
+ std::pair<SDOperand, SDOperand>
+ LowerCCCCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg,
+ bool isTailCall,
+ SDOperand Callee, ArgListTy &Args, SelectionDAG &DAG);
+
+ // Fast Calling Convention implementation.
+ std::vector<SDOperand> LowerFastCCArguments(Function &F, SelectionDAG &DAG);
+ std::pair<SDOperand, SDOperand>
+ LowerFastCCCallTo(SDOperand Chain, const Type *RetTy, bool isTailCall,
+ SDOperand Callee, ArgListTy &Args, SelectionDAG &DAG);
};
}
-
std::vector<SDOperand>
X86TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
+ if (F.getCallingConv() == CallingConv::Fast && EnableFastCC)
+ return LowerFastCCArguments(F, DAG);
+ return LowerCCCArguments(F, DAG);
+}
+
+std::pair<SDOperand, SDOperand>
+X86TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
+ bool isVarArg, unsigned CallingConv,
+ bool isTailCall,
+ SDOperand Callee, ArgListTy &Args,
+ SelectionDAG &DAG) {
+ assert((!isVarArg || CallingConv == CallingConv::C) &&
+ "Only C takes varargs!");
+ if (CallingConv == CallingConv::Fast && EnableFastCC)
+ return LowerFastCCCallTo(Chain, RetTy, isTailCall, Callee, Args, DAG);
+ return LowerCCCCallTo(Chain, RetTy, isVarArg, isTailCall, Callee, Args, DAG);
+}
+
+//===----------------------------------------------------------------------===//
+// C Calling Convention implementation
+//===----------------------------------------------------------------------===//
+
+std::vector<SDOperand>
+X86TargetLowering::LowerCCCArguments(Function &F, SelectionDAG &DAG) {
std::vector<SDOperand> ArgValues;
+ MachineFunction &MF = DAG.getMachineFunction();
+ MachineFrameInfo *MFI = MF.getFrameInfo();
+
// Add DAG nodes to load the arguments... On entry to a function on the X86,
// the stack frame looks like this:
//
// [ESP] -- return address
// [ESP + 4] -- first argument (leftmost lexically)
// [ESP + 8] -- second argument, if first argument is four bytes in size
- // ...
+ // ...
//
- MachineFunction &MF = DAG.getMachineFunction();
- MachineFrameInfo *MFI = MF.getFrameInfo();
-
unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
- for (Function::aiterator I = F.abegin(), E = F.aend(); I != E; ++I) {
+ for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
MVT::ValueType ObjectVT = getValueType(I->getType());
unsigned ArgIncrement = 4;
unsigned ObjSize;
}
// Create the frame index object for this incoming parameter...
int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
-
+
// Create the SelectionDAG nodes corresponding to a load from this parameter
SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
// dead loads.
SDOperand ArgValue;
if (!I->use_empty())
- ArgValue = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN);
+ ArgValue = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN,
+ DAG.getSrcValue(NULL));
else {
if (MVT::isInteger(ObjectVT))
ArgValue = DAG.getConstant(0, ObjectVT);
// the start of the first vararg value... for expansion of llvm.va_start.
if (F.isVarArg())
VarArgsFrameIndex = MFI->CreateFixedObject(1, ArgOffset);
- ReturnAddrIndex = 0; // No return address slot generated yet.
+ ReturnAddrIndex = 0; // No return address slot generated yet.
+ BytesToPopOnReturn = 0; // Callee pops nothing.
+ BytesCallerReserves = ArgOffset;
+
+ // Finally, inform the code generator which regs we return values in.
+ switch (getValueType(F.getReturnType())) {
+ default: assert(0 && "Unknown type!");
+ case MVT::isVoid: break;
+ case MVT::i1:
+ case MVT::i8:
+ case MVT::i16:
+ case MVT::i32:
+ MF.addLiveOut(X86::EAX);
+ break;
+ case MVT::i64:
+ MF.addLiveOut(X86::EAX);
+ MF.addLiveOut(X86::EDX);
+ break;
+ case MVT::f32:
+ case MVT::f64:
+ MF.addLiveOut(X86::ST0);
+ break;
+ }
return ArgValues;
}
std::pair<SDOperand, SDOperand>
-X86TargetLowering::LowerCallTo(SDOperand Chain,
- const Type *RetTy, SDOperand Callee,
- ArgListTy &Args, SelectionDAG &DAG) {
+X86TargetLowering::LowerCCCCallTo(SDOperand Chain, const Type *RetTy,
+ bool isVarArg, bool isTailCall,
+ SDOperand Callee, ArgListTy &Args,
+ SelectionDAG &DAG) {
// Count how many bytes are to be pushed on the stack.
unsigned NumBytes = 0;
if (Args.empty()) {
// Save zero bytes.
- Chain = DAG.getNode(ISD::ADJCALLSTACKDOWN, MVT::Other, Chain,
+ Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain,
DAG.getConstant(0, getPointerTy()));
} else {
for (unsigned i = 0, e = Args.size(); i != e; ++i)
break;
}
- Chain = DAG.getNode(ISD::ADJCALLSTACKDOWN, MVT::Other, Chain,
+ Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain,
DAG.getConstant(NumBytes, getPointerTy()));
// Arguments go on the stack in reverse order, as specified by the ABI.
unsigned ArgOffset = 0;
- SDOperand StackPtr = DAG.getCopyFromReg(X86::ESP, MVT::i32,
- DAG.getEntryNode());
+ SDOperand StackPtr = DAG.getCopyFromReg(DAG.getEntryNode(),
+ X86::ESP, MVT::i32);
+ std::vector<SDOperand> Stores;
+
for (unsigned i = 0, e = Args.size(); i != e; ++i) {
- unsigned ArgReg;
SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
// FALL THROUGH
case MVT::i32:
case MVT::f32:
- // FIXME: Note that all of these stores are independent of each other.
- Chain = DAG.getNode(ISD::STORE, MVT::Other, Chain,
- Args[i].first, PtrOff);
+ Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
+ Args[i].first, PtrOff,
+ DAG.getSrcValue(NULL)));
ArgOffset += 4;
break;
case MVT::i64:
case MVT::f64:
- // FIXME: Note that all of these stores are independent of each other.
- Chain = DAG.getNode(ISD::STORE, MVT::Other, Chain,
- Args[i].first, PtrOff);
+ Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
+ Args[i].first, PtrOff,
+ DAG.getSrcValue(NULL)));
ArgOffset += 8;
break;
}
}
+ Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores);
}
std::vector<MVT::ValueType> RetVals;
MVT::ValueType RetTyVT = getValueType(RetTy);
- if (RetTyVT != MVT::isVoid)
- RetVals.push_back(RetTyVT);
RetVals.push_back(MVT::Other);
- SDOperand TheCall = SDOperand(DAG.getCall(RetVals, Chain, Callee), 0);
- Chain = TheCall.getValue(RetTyVT != MVT::isVoid);
- Chain = DAG.getNode(ISD::ADJCALLSTACKUP, MVT::Other, Chain,
- DAG.getConstant(NumBytes, getPointerTy()));
- return std::make_pair(TheCall, Chain);
+ // The result values produced have to be legal. Promote the result.
+ switch (RetTyVT) {
+ case MVT::isVoid: break;
+ default:
+ RetVals.push_back(RetTyVT);
+ break;
+ case MVT::i1:
+ case MVT::i8:
+ case MVT::i16:
+ RetVals.push_back(MVT::i32);
+ break;
+ case MVT::f32:
+ if (X86ScalarSSE)
+ RetVals.push_back(MVT::f32);
+ else
+ RetVals.push_back(MVT::f64);
+ break;
+ case MVT::i64:
+ RetVals.push_back(MVT::i32);
+ RetVals.push_back(MVT::i32);
+ break;
+ }
+ std::vector<SDOperand> Ops;
+ Ops.push_back(Chain);
+ Ops.push_back(Callee);
+ Ops.push_back(DAG.getConstant(NumBytes, getPointerTy()));
+ Ops.push_back(DAG.getConstant(0, getPointerTy()));
+ SDOperand TheCall = DAG.getNode(isTailCall ? X86ISD::TAILCALL : X86ISD::CALL,
+ RetVals, Ops);
+ Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, TheCall);
+
+ SDOperand ResultVal;
+ switch (RetTyVT) {
+ case MVT::isVoid: break;
+ default:
+ ResultVal = TheCall.getValue(1);
+ break;
+ case MVT::i1:
+ case MVT::i8:
+ case MVT::i16:
+ ResultVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, TheCall.getValue(1));
+ break;
+ case MVT::f32:
+ // FIXME: we would really like to remember that this FP_ROUND operation is
+ // okay to eliminate if we allow excess FP precision.
+ ResultVal = DAG.getNode(ISD::FP_ROUND, MVT::f32, TheCall.getValue(1));
+ break;
+ case MVT::i64:
+ ResultVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, TheCall.getValue(1),
+ TheCall.getValue(2));
+ break;
+ }
+
+ return std::make_pair(ResultVal, Chain);
}
-std::pair<SDOperand, SDOperand>
-X86TargetLowering::LowerVAStart(SDOperand Chain, SelectionDAG &DAG) {
- // vastart just returns the address of the VarArgsFrameIndex slot.
- return std::make_pair(DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32), Chain);
+SDOperand
+X86TargetLowering::LowerVAStart(SDOperand Chain, SDOperand VAListP,
+ Value *VAListV, SelectionDAG &DAG) {
+ // vastart just stores the address of the VarArgsFrameIndex slot.
+ SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32);
+ return DAG.getNode(ISD::STORE, MVT::Other, Chain, FR, VAListP,
+ DAG.getSrcValue(VAListV));
}
-std::pair<SDOperand,SDOperand> X86TargetLowering::
-LowerVAArgNext(bool isVANext, SDOperand Chain, SDOperand VAList,
- const Type *ArgTy, SelectionDAG &DAG) {
+
+std::pair<SDOperand,SDOperand>
+X86TargetLowering::LowerVAArg(SDOperand Chain, SDOperand VAListP,
+ Value *VAListV, const Type *ArgTy,
+ SelectionDAG &DAG) {
MVT::ValueType ArgVT = getValueType(ArgTy);
- SDOperand Result;
- if (!isVANext) {
- Result = DAG.getLoad(ArgVT, DAG.getEntryNode(), VAList);
- } else {
- unsigned Amt;
- if (ArgVT == MVT::i32)
- Amt = 4;
- else {
- assert((ArgVT == MVT::i64 || ArgVT == MVT::f64) &&
- "Other types should have been promoted for varargs!");
- Amt = 8;
- }
- Result = DAG.getNode(ISD::ADD, VAList.getValueType(), VAList,
- DAG.getConstant(Amt, VAList.getValueType()));
+ SDOperand Val = DAG.getLoad(MVT::i32, Chain,
+ VAListP, DAG.getSrcValue(VAListV));
+ SDOperand Result = DAG.getLoad(ArgVT, Chain, Val,
+ DAG.getSrcValue(NULL));
+ unsigned Amt;
+ if (ArgVT == MVT::i32)
+ Amt = 4;
+ else {
+ assert((ArgVT == MVT::i64 || ArgVT == MVT::f64) &&
+ "Other types should have been promoted for varargs!");
+ Amt = 8;
}
+ Val = DAG.getNode(ISD::ADD, Val.getValueType(), Val,
+ DAG.getConstant(Amt, Val.getValueType()));
+ Chain = DAG.getNode(ISD::STORE, MVT::Other, Chain,
+ Val, VAListP, DAG.getSrcValue(VAListV));
return std::make_pair(Result, Chain);
}
-
+
+//===----------------------------------------------------------------------===//
+// Fast Calling Convention implementation
+//===----------------------------------------------------------------------===//
+//
+// The X86 'fast' calling convention passes up to two integer arguments in
+// registers (an appropriate portion of EAX/EDX), passes arguments in C order,
+// and requires that the callee pop its arguments off the stack (allowing proper
+// tail calls), and has the same return value conventions as C calling convs.
+//
+// This calling convention always arranges for the callee pop value to be 8n+4
+// bytes, which is needed for tail recursion elimination and stack alignment
+// reasons.
+//
+// Note that this can be enhanced in the future to pass fp vals in registers
+// (when we have a global fp allocator) and do other tricks.
+//
+
+/// AddLiveIn - This helper function adds the specified physical register to the
+/// MachineFunction as a live in value. It also creates a corresponding virtual
+/// register for it.
+static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg,
+ TargetRegisterClass *RC) {
+ assert(RC->contains(PReg) && "Not the correct regclass!");
+ unsigned VReg = MF.getSSARegMap()->createVirtualRegister(RC);
+ MF.addLiveIn(PReg, VReg);
+ return VReg;
+}
+
+
+std::vector<SDOperand>
+X86TargetLowering::LowerFastCCArguments(Function &F, SelectionDAG &DAG) {
+ std::vector<SDOperand> ArgValues;
+
+ MachineFunction &MF = DAG.getMachineFunction();
+ MachineFrameInfo *MFI = MF.getFrameInfo();
+
+ // Add DAG nodes to load the arguments... On entry to a function the stack
+ // frame looks like this:
+ //
+ // [ESP] -- return address
+ // [ESP + 4] -- first nonreg argument (leftmost lexically)
+ // [ESP + 8] -- second nonreg argument, if first argument is 4 bytes in size
+ // ...
+ unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
+
+ // Keep track of the number of integer regs passed so far. This can be either
+ // 0 (neither EAX or EDX used), 1 (EAX is used) or 2 (EAX and EDX are both
+ // used).
+ unsigned NumIntRegs = 0;
+
+ for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
+ MVT::ValueType ObjectVT = getValueType(I->getType());
+ unsigned ArgIncrement = 4;
+ unsigned ObjSize = 0;
+ SDOperand ArgValue;
+
+ switch (ObjectVT) {
+ default: assert(0 && "Unhandled argument type!");
+ case MVT::i1:
+ case MVT::i8:
+ if (NumIntRegs < 2) {
+ if (!I->use_empty()) {
+ unsigned VReg = AddLiveIn(MF, NumIntRegs ? X86::DL : X86::AL,
+ X86::R8RegisterClass);
+ ArgValue = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i8);
+ DAG.setRoot(ArgValue.getValue(1));
+ }
+ ++NumIntRegs;
+ break;
+ }
+
+ ObjSize = 1;
+ break;
+ case MVT::i16:
+ if (NumIntRegs < 2) {
+ if (!I->use_empty()) {
+ unsigned VReg = AddLiveIn(MF, NumIntRegs ? X86::DX : X86::AX,
+ X86::R16RegisterClass);
+ ArgValue = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i16);
+ DAG.setRoot(ArgValue.getValue(1));
+ }
+ ++NumIntRegs;
+ break;
+ }
+ ObjSize = 2;
+ break;
+ case MVT::i32:
+ if (NumIntRegs < 2) {
+ if (!I->use_empty()) {
+ unsigned VReg = AddLiveIn(MF,NumIntRegs ? X86::EDX : X86::EAX,
+ X86::R32RegisterClass);
+ ArgValue = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32);
+ DAG.setRoot(ArgValue.getValue(1));
+ }
+ ++NumIntRegs;
+ break;
+ }
+ ObjSize = 4;
+ break;
+ case MVT::i64:
+ if (NumIntRegs == 0) {
+ if (!I->use_empty()) {
+ unsigned BotReg = AddLiveIn(MF, X86::EAX, X86::R32RegisterClass);
+ unsigned TopReg = AddLiveIn(MF, X86::EDX, X86::R32RegisterClass);
+
+ SDOperand Low = DAG.getCopyFromReg(DAG.getRoot(), BotReg, MVT::i32);
+ SDOperand Hi = DAG.getCopyFromReg(Low.getValue(1), TopReg, MVT::i32);
+ DAG.setRoot(Hi.getValue(1));
+
+ ArgValue = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Low, Hi);
+ }
+ NumIntRegs = 2;
+ break;
+ } else if (NumIntRegs == 1) {
+ if (!I->use_empty()) {
+ unsigned BotReg = AddLiveIn(MF, X86::EDX, X86::R32RegisterClass);
+ SDOperand Low = DAG.getCopyFromReg(DAG.getRoot(), BotReg, MVT::i32);
+ DAG.setRoot(Low.getValue(1));
+
+ // Load the high part from memory.
+ // Create the frame index object for this incoming parameter...
+ int FI = MFI->CreateFixedObject(4, ArgOffset);
+ SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
+ SDOperand Hi = DAG.getLoad(MVT::i32, DAG.getEntryNode(), FIN,
+ DAG.getSrcValue(NULL));
+ ArgValue = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Low, Hi);
+ }
+ ArgOffset += 4;
+ NumIntRegs = 2;
+ break;
+ }
+ ObjSize = ArgIncrement = 8;
+ break;
+ case MVT::f32: ObjSize = 4; break;
+ case MVT::f64: ObjSize = ArgIncrement = 8; break;
+ }
+
+ // Don't codegen dead arguments. FIXME: remove this check when we can nuke
+ // dead loads.
+ if (ObjSize && !I->use_empty()) {
+ // Create the frame index object for this incoming parameter...
+ int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
+
+ // Create the SelectionDAG nodes corresponding to a load from this
+ // parameter.
+ SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
+
+ ArgValue = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN,
+ DAG.getSrcValue(NULL));
+ } else if (ArgValue.Val == 0) {
+ if (MVT::isInteger(ObjectVT))
+ ArgValue = DAG.getConstant(0, ObjectVT);
+ else
+ ArgValue = DAG.getConstantFP(0, ObjectVT);
+ }
+ ArgValues.push_back(ArgValue);
+
+ if (ObjSize)
+ ArgOffset += ArgIncrement; // Move on to the next argument.
+ }
+
+ // Make sure the instruction takes 8n+4 bytes to make sure the start of the
+ // arguments and the arguments after the retaddr has been pushed are aligned.
+ if ((ArgOffset & 7) == 0)
+ ArgOffset += 4;
+
+ VarArgsFrameIndex = 0xAAAAAAA; // fastcc functions can't have varargs.
+ ReturnAddrIndex = 0; // No return address slot generated yet.
+ BytesToPopOnReturn = ArgOffset; // Callee pops all stack arguments.
+ BytesCallerReserves = 0;
+
+ // Finally, inform the code generator which regs we return values in.
+ switch (getValueType(F.getReturnType())) {
+ default: assert(0 && "Unknown type!");
+ case MVT::isVoid: break;
+ case MVT::i1:
+ case MVT::i8:
+ case MVT::i16:
+ case MVT::i32:
+ MF.addLiveOut(X86::EAX);
+ break;
+ case MVT::i64:
+ MF.addLiveOut(X86::EAX);
+ MF.addLiveOut(X86::EDX);
+ break;
+ case MVT::f32:
+ case MVT::f64:
+ MF.addLiveOut(X86::ST0);
+ break;
+ }
+ return ArgValues;
+}
+
+std::pair<SDOperand, SDOperand>
+X86TargetLowering::LowerFastCCCallTo(SDOperand Chain, const Type *RetTy,
+ bool isTailCall, SDOperand Callee,
+ ArgListTy &Args, SelectionDAG &DAG) {
+ // Count how many bytes are to be pushed on the stack.
+ unsigned NumBytes = 0;
+
+ // Keep track of the number of integer regs passed so far. This can be either
+ // 0 (neither EAX or EDX used), 1 (EAX is used) or 2 (EAX and EDX are both
+ // used).
+ unsigned NumIntRegs = 0;
+
+ for (unsigned i = 0, e = Args.size(); i != e; ++i)
+ switch (getValueType(Args[i].second)) {
+ default: assert(0 && "Unknown value type!");
+ case MVT::i1:
+ case MVT::i8:
+ case MVT::i16:
+ case MVT::i32:
+ if (NumIntRegs < 2) {
+ ++NumIntRegs;
+ break;
+ }
+ // fall through
+ case MVT::f32:
+ NumBytes += 4;
+ break;
+ case MVT::i64:
+ if (NumIntRegs == 0) {
+ NumIntRegs = 2;
+ break;
+ } else if (NumIntRegs == 1) {
+ NumIntRegs = 2;
+ NumBytes += 4;
+ break;
+ }
+
+ // fall through
+ case MVT::f64:
+ NumBytes += 8;
+ break;
+ }
+
+ // Make sure the instruction takes 8n+4 bytes to make sure the start of the
+ // arguments and the arguments after the retaddr has been pushed are aligned.
+ if ((NumBytes & 7) == 0)
+ NumBytes += 4;
+
+ Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain,
+ DAG.getConstant(NumBytes, getPointerTy()));
+
+ // Arguments go on the stack in reverse order, as specified by the ABI.
+ unsigned ArgOffset = 0;
+ SDOperand StackPtr = DAG.getCopyFromReg(DAG.getEntryNode(),
+ X86::ESP, MVT::i32);
+ NumIntRegs = 0;
+ std::vector<SDOperand> Stores;
+ std::vector<SDOperand> RegValuesToPass;
+ for (unsigned i = 0, e = Args.size(); i != e; ++i) {
+ switch (getValueType(Args[i].second)) {
+ default: assert(0 && "Unexpected ValueType for argument!");
+ case MVT::i1:
+ case MVT::i8:
+ case MVT::i16:
+ case MVT::i32:
+ if (NumIntRegs < 2) {
+ RegValuesToPass.push_back(Args[i].first);
+ ++NumIntRegs;
+ break;
+ }
+ // Fall through
+ case MVT::f32: {
+ SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
+ PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
+ Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
+ Args[i].first, PtrOff,
+ DAG.getSrcValue(NULL)));
+ ArgOffset += 4;
+ break;
+ }
+ case MVT::i64:
+ if (NumIntRegs < 2) { // Can pass part of it in regs?
+ SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
+ Args[i].first, DAG.getConstant(1, MVT::i32));
+ SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
+ Args[i].first, DAG.getConstant(0, MVT::i32));
+ RegValuesToPass.push_back(Lo);
+ ++NumIntRegs;
+ if (NumIntRegs < 2) { // Pass both parts in regs?
+ RegValuesToPass.push_back(Hi);
+ ++NumIntRegs;
+ } else {
+ // Pass the high part in memory.
+ SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
+ PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
+ Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
+ Hi, PtrOff, DAG.getSrcValue(NULL)));
+ ArgOffset += 4;
+ }
+ break;
+ }
+ // Fall through
+ case MVT::f64:
+ SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
+ PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
+ Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
+ Args[i].first, PtrOff,
+ DAG.getSrcValue(NULL)));
+ ArgOffset += 8;
+ break;
+ }
+ }
+ if (!Stores.empty())
+ Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores);
+
+ // Make sure the instruction takes 8n+4 bytes to make sure the start of the
+ // arguments and the arguments after the retaddr has been pushed are aligned.
+ if ((ArgOffset & 7) == 0)
+ ArgOffset += 4;
+
+ std::vector<MVT::ValueType> RetVals;
+ MVT::ValueType RetTyVT = getValueType(RetTy);
+
+ RetVals.push_back(MVT::Other);
+
+ // The result values produced have to be legal. Promote the result.
+ switch (RetTyVT) {
+ case MVT::isVoid: break;
+ default:
+ RetVals.push_back(RetTyVT);
+ break;
+ case MVT::i1:
+ case MVT::i8:
+ case MVT::i16:
+ RetVals.push_back(MVT::i32);
+ break;
+ case MVT::f32:
+ if (X86ScalarSSE)
+ RetVals.push_back(MVT::f32);
+ else
+ RetVals.push_back(MVT::f64);
+ break;
+ case MVT::i64:
+ RetVals.push_back(MVT::i32);
+ RetVals.push_back(MVT::i32);
+ break;
+ }
+
+ std::vector<SDOperand> Ops;
+ Ops.push_back(Chain);
+ Ops.push_back(Callee);
+ Ops.push_back(DAG.getConstant(ArgOffset, getPointerTy()));
+ // Callee pops all arg values on the stack.
+ Ops.push_back(DAG.getConstant(ArgOffset, getPointerTy()));
+
+ // Pass register arguments as needed.
+ Ops.insert(Ops.end(), RegValuesToPass.begin(), RegValuesToPass.end());
+
+ SDOperand TheCall = DAG.getNode(isTailCall ? X86ISD::TAILCALL : X86ISD::CALL,
+ RetVals, Ops);
+ Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, TheCall);
+
+ SDOperand ResultVal;
+ switch (RetTyVT) {
+ case MVT::isVoid: break;
+ default:
+ ResultVal = TheCall.getValue(1);
+ break;
+ case MVT::i1:
+ case MVT::i8:
+ case MVT::i16:
+ ResultVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, TheCall.getValue(1));
+ break;
+ case MVT::f32:
+ // FIXME: we would really like to remember that this FP_ROUND operation is
+ // okay to eliminate if we allow excess FP precision.
+ ResultVal = DAG.getNode(ISD::FP_ROUND, MVT::f32, TheCall.getValue(1));
+ break;
+ case MVT::i64:
+ ResultVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, TheCall.getValue(1),
+ TheCall.getValue(2));
+ break;
+ }
+
+ return std::make_pair(ResultVal, Chain);
+}
+
+SDOperand X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) {
+ if (ReturnAddrIndex == 0) {
+ // Set up a frame object for the return address.
+ MachineFunction &MF = DAG.getMachineFunction();
+ ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(4, -4);
+ }
+
+ return DAG.getFrameIndex(ReturnAddrIndex, MVT::i32);
+}
+
+
std::pair<SDOperand, SDOperand> X86TargetLowering::
LowerFrameReturnAddress(bool isFrameAddress, SDOperand Chain, unsigned Depth,
if (Depth) // Depths > 0 not supported yet!
Result = DAG.getConstant(0, getPointerTy());
else {
- if (ReturnAddrIndex == 0) {
- // Set up a frame object for the return address.
- MachineFunction &MF = DAG.getMachineFunction();
- ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(4, -4);
- }
-
- SDOperand RetAddrFI = DAG.getFrameIndex(ReturnAddrIndex, MVT::i32);
-
+ SDOperand RetAddrFI = getReturnAddressFrameIndex(DAG);
if (!isFrameAddress)
// Just load the return address
- Result = DAG.getLoad(MVT::i32, DAG.getEntryNode(), RetAddrFI);
+ Result = DAG.getLoad(MVT::i32, DAG.getEntryNode(), RetAddrFI,
+ DAG.getSrcValue(NULL));
else
Result = DAG.getNode(ISD::SUB, MVT::i32, RetAddrFI,
DAG.getConstant(4, MVT::i32));
return std::make_pair(Result, Chain);
}
+//===----------------------------------------------------------------------===//
+// X86 Custom Lowering Hooks
+//===----------------------------------------------------------------------===//
+
+/// LowerOperation - Provide custom lowering hooks for some operations.
+///
+SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
+ switch (Op.getOpcode()) {
+ default: assert(0 && "Should not custom lower this!");
+ case ISD::SINT_TO_FP: {
+ assert(Op.getValueType() == MVT::f64 &&
+ Op.getOperand(0).getValueType() == MVT::i64 &&
+ "Unknown SINT_TO_FP to lower!");
+ // We lower sint64->FP into a store to a temporary stack slot, followed by a
+ // FILD64m node.
+ MachineFunction &MF = DAG.getMachineFunction();
+ int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
+ SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
+ SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
+ Op.getOperand(0), StackSlot, DAG.getSrcValue(NULL));
+ std::vector<MVT::ValueType> RTs;
+ RTs.push_back(MVT::f64);
+ RTs.push_back(MVT::Other);
+ std::vector<SDOperand> Ops;
+ Ops.push_back(Store);
+ Ops.push_back(StackSlot);
+ return DAG.getNode(X86ISD::FILD64m, RTs, Ops);
+ }
+ case ISD::FP_TO_SINT: {
+ assert(Op.getValueType() <= MVT::i64 && Op.getValueType() >= MVT::i16 &&
+ Op.getOperand(0).getValueType() == MVT::f64 &&
+ "Unknown FP_TO_SINT to lower!");
+ // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
+ // stack slot.
+ MachineFunction &MF = DAG.getMachineFunction();
+ unsigned MemSize = MVT::getSizeInBits(Op.getValueType())/8;
+ int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
+ SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
+
+ unsigned Opc;
+ switch (Op.getValueType()) {
+ default: assert(0 && "Invalid FP_TO_SINT to lower!");
+ case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
+ case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
+ case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
+ }
+
+ // Build the FP_TO_INT*_IN_MEM
+ std::vector<SDOperand> Ops;
+ Ops.push_back(DAG.getEntryNode());
+ Ops.push_back(Op.getOperand(0));
+ Ops.push_back(StackSlot);
+ SDOperand FIST = DAG.getNode(Opc, MVT::Other, Ops);
+
+ // Load the result.
+ return DAG.getLoad(Op.getValueType(), FIST, StackSlot,
+ DAG.getSrcValue(NULL));
+ }
+ }
+}
+
+
+//===----------------------------------------------------------------------===//
+// Pattern Matcher Implementation
+//===----------------------------------------------------------------------===//
namespace {
/// X86ISelAddressMode - This corresponds to X86AddressMode, but uses
RegBase,
FrameIndexBase,
} BaseType;
-
+
struct { // This is really a union, discriminated by BaseType!
SDOperand Reg;
int FrameIndex;
} Base;
-
+
unsigned Scale;
SDOperand IndexReg;
unsigned Disp;
GlobalValue *GV;
-
+
X86ISelAddressMode()
: BaseType(RegBase), Scale(1), IndexReg(), Disp(), GV(0) {
}
/// tree.
std::map<SDOperand, unsigned> ExprMap;
+ /// TheDAG - The DAG being selected during Select* operations.
+ SelectionDAG *TheDAG;
+
+ /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
+ /// make the right decision when generating code for different targets.
+ const X86Subtarget *Subtarget;
public:
ISel(TargetMachine &TM) : SelectionDAGISel(X86Lowering), X86Lowering(TM) {
+ Subtarget = &TM.getSubtarget<X86Subtarget>();
+ }
+
+ virtual const char *getPassName() const {
+ return "X86 Pattern Instruction Selection";
}
unsigned getRegPressure(SDOperand O) {
/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
- bool isFoldableLoad(SDOperand Op, SDOperand OtherOp);
+ virtual void EmitFunctionEntryCode(Function &Fn, MachineFunction &MF);
+
+ bool isFoldableLoad(SDOperand Op, SDOperand OtherOp,
+ bool FloatPromoteOk = false);
void EmitFoldedLoad(SDOperand Op, X86AddressMode &AM);
bool TryToFoldLoadOpStore(SDNode *Node);
-
bool EmitOrOpOp(SDOperand Op1, SDOperand Op2, unsigned DestReg);
void EmitCMP(SDOperand LHS, SDOperand RHS, bool isOnlyUse);
bool EmitBranchCC(MachineBasicBlock *Dest, SDOperand Chain, SDOperand Cond);
- void EmitSelectCC(SDOperand Cond, MVT::ValueType SVT,
- unsigned RTrue, unsigned RFalse, unsigned RDest);
+ void EmitSelectCC(SDOperand Cond, SDOperand True, SDOperand False,
+ MVT::ValueType SVT, unsigned RDest);
unsigned SelectExpr(SDOperand N);
X86AddressMode SelectAddrExprs(const X86ISelAddressMode &IAM);
bool MatchAddress(SDOperand N, X86ISelAddressMode &AM);
void SelectAddress(SDOperand N, X86AddressMode &AM);
+ bool EmitPotentialTailCall(SDNode *Node);
+ void EmitFastCCToFastCCTailCall(SDNode *TailCallNode);
void Select(SDOperand N);
};
}
+/// EmitSpecialCodeForMain - Emit any code that needs to be executed only in
+/// the main function.
+static void EmitSpecialCodeForMain(MachineBasicBlock *BB,
+ MachineFrameInfo *MFI) {
+ // Switch the FPU to 64-bit precision mode for better compatibility and speed.
+ int CWFrameIdx = MFI->CreateStackObject(2, 2);
+ addFrameReference(BuildMI(BB, X86::FNSTCW16m, 4), CWFrameIdx);
+
+ // Set the high part to be 64-bit precision.
+ addFrameReference(BuildMI(BB, X86::MOV8mi, 5),
+ CWFrameIdx, 1).addImm(2);
+
+ // Reload the modified control word now.
+ addFrameReference(BuildMI(BB, X86::FLDCW16m, 4), CWFrameIdx);
+}
+
+void ISel::EmitFunctionEntryCode(Function &Fn, MachineFunction &MF) {
+ // If this is main, emit special code for main.
+ MachineBasicBlock *BB = MF.begin();
+ if (Fn.hasExternalLinkage() && Fn.getName() == "main")
+ EmitSpecialCodeForMain(BB, MF.getFrameInfo());
+}
+
+
/// InstructionSelectBasicBlock - This callback is invoked by SelectionDAGISel
/// when it has created a SelectionDAG for us to codegen.
void ISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
// While we're doing this, keep track of whether we see any FP code for
// FP_REG_KILL insertion.
ContainsFPCode = false;
+ MachineFunction *MF = BB->getParent();
// Scan the PHI nodes that already are inserted into this basic block. If any
// of them is a PHI of a floating point value, we need to insert an
// FP_REG_KILL.
- SSARegMap *RegMap = BB->getParent()->getSSARegMap();
- for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end();
- I != E; ++I) {
- assert(I->getOpcode() == X86::PHI &&
- "Isn't just PHI nodes?");
- if (RegMap->getRegClass(I->getOperand(0).getReg()) ==
- X86::RFPRegisterClass) {
- ContainsFPCode = true;
- break;
+ SSARegMap *RegMap = MF->getSSARegMap();
+ if (BB != MF->begin())
+ for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end();
+ I != E; ++I) {
+ assert(I->getOpcode() == X86::PHI &&
+ "Isn't just PHI nodes?");
+ if (RegMap->getRegClass(I->getOperand(0).getReg()) ==
+ X86::RFPRegisterClass) {
+ ContainsFPCode = true;
+ break;
+ }
}
- }
// Compute the RegPressureMap, which is an approximation for the number of
// registers required to compute each node.
ComputeRegPressure(DAG.getRoot());
+ TheDAG = &DAG;
+
// Codegen the basic block.
Select(DAG.getRoot());
+ TheDAG = 0;
+
// Finally, look at all of the successors of this block. If any contain a PHI
// node of FP type, we need to insert an FP_REG_KILL in this block.
for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(),
break;
}
}
-
+
+ // Final check, check LLVM BB's that are successors to the LLVM BB
+ // corresponding to BB for FP PHI nodes.
+ const BasicBlock *LLVMBB = BB->getBasicBlock();
+ const PHINode *PN;
+ if (!ContainsFPCode)
+ for (succ_const_iterator SI = succ_begin(LLVMBB), E = succ_end(LLVMBB);
+ SI != E && !ContainsFPCode; ++SI)
+ for (BasicBlock::const_iterator II = SI->begin();
+ (PN = dyn_cast<PHINode>(II)); ++II)
+ if (PN->getType()->isFloatingPoint()) {
+ ContainsFPCode = true;
+ break;
+ }
+
+
// Insert FP_REG_KILL instructions into basic blocks that need them. This
// only occurs due to the floating point stackifier not being aggressive
// enough to handle arbitrary global stackification.
// basic blocks. This will be a huge win, but we are waiting on the global
// allocators before we can do this.
//
- if (ContainsFPCode && BB->succ_size()) {
+ if (ContainsFPCode) {
BuildMI(*BB, BB->getFirstTerminator(), X86::FP_REG_KILL, 0);
++NumFPKill;
}
-
+
// Clear state used for selection.
ExprMap.clear();
RegPressureMap.clear();
std::set<SDNode*> &Visited) {
if (N == Op) return true; // Found it.
SDNode *Node = N.Val;
- if (Node->getNumOperands() == 0) return false; // Leaf?
+ if (Node->getNumOperands() == 0 || // Leaf?
+ Node->getNodeDepth() <= Op.getNodeDepth()) return false; // Can't find it?
if (!Visited.insert(Node).second) return false; // Already visited?
// Recurse for the first N-1 operands.
} else if (IAM.IndexReg.Val) {
Result.IndexReg = SelectExpr(IAM.IndexReg);
}
-
+
switch (IAM.BaseType) {
case X86ISelAddressMode::RegBase:
Result.BaseType = X86AddressMode::RegBase;
break;
case ISD::GlobalAddress:
if (AM.GV == 0) {
- AM.GV = cast<GlobalAddressSDNode>(N)->getGlobal();
- return false;
+ GlobalValue *GV = cast<GlobalAddressSDNode>(N)->getGlobal();
+ // For Darwin, external and weak symbols are indirect, so we want to load
+ // the value at address GV, not the value of GV itself. This means that
+ // the GlobalAddress must be in the base or index register of the address,
+ // not the GV offset field.
+ if (Subtarget->getIndirectExternAndWeakGlobals() &&
+ (GV->hasWeakLinkage() || GV->isExternal())) {
+ break;
+ } else {
+ AM.GV = GV;
+ return false;
+ }
}
break;
case ISD::Constant:
ConstantSDNode *AddVal =
cast<ConstantSDNode>(MulVal.Val->getOperand(1));
AM.Disp += AddVal->getValue() * CN->getValue();
- } else {
+ } else {
Reg = N.Val->getOperand(0);
}
return false;
}
- SetCCSDNode *SetCC = dyn_cast<SetCCSDNode>(Cond);
- if (SetCC == 0)
+ if (Cond.getOpcode() != ISD::SETCC)
return true; // Can only handle simple setcc's so far.
+ ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
unsigned Opc;
// Handle integer conditions first.
- if (MVT::isInteger(SetCC->getOperand(0).getValueType())) {
- switch (SetCC->getCondition()) {
+ if (MVT::isInteger(Cond.getOperand(0).getValueType())) {
+ switch (CC) {
default: assert(0 && "Illegal integer SetCC!");
case ISD::SETEQ: Opc = X86::JE; break;
case ISD::SETGT: Opc = X86::JG; break;
case ISD::SETUGE: Opc = X86::JAE; break;
}
Select(Chain);
- EmitCMP(SetCC->getOperand(0), SetCC->getOperand(1), SetCC->hasOneUse());
+ EmitCMP(Cond.getOperand(0), Cond.getOperand(1), Cond.hasOneUse());
BuildMI(BB, Opc, 1).addMBB(Dest);
return false;
}
// 1 | 0 | 0 | X == Y
// 1 | 1 | 1 | unordered
//
- switch (SetCC->getCondition()) {
+ switch (CC) {
default: assert(0 && "Invalid FP setcc!");
case ISD::SETUEQ:
case ISD::SETEQ: Opc = X86::JE; break; // True if ZF = 1
}
Select(Chain);
- EmitCMP(SetCC->getOperand(0), SetCC->getOperand(1), SetCC->hasOneUse());
+ EmitCMP(Cond.getOperand(0), Cond.getOperand(1), Cond.hasOneUse());
BuildMI(BB, Opc, 1).addMBB(Dest);
if (Opc2)
BuildMI(BB, Opc2, 1).addMBB(Dest);
}
/// EmitSelectCC - Emit code into BB that performs a select operation between
-/// the two registers RTrue and RFalse, generating a result into RDest. Return
-/// true if the fold cannot be performed.
+/// the two registers RTrue and RFalse, generating a result into RDest.
///
-void ISel::EmitSelectCC(SDOperand Cond, MVT::ValueType SVT,
- unsigned RTrue, unsigned RFalse, unsigned RDest) {
+void ISel::EmitSelectCC(SDOperand Cond, SDOperand True, SDOperand False,
+ MVT::ValueType SVT, unsigned RDest) {
+ unsigned RTrue, RFalse;
enum Condition {
EQ, NE, LT, LE, GT, GE, B, BE, A, AE, P, NP,
NOT_SET
static const unsigned CMOVTAB16[] = {
X86::CMOVE16rr, X86::CMOVNE16rr, X86::CMOVL16rr, X86::CMOVLE16rr,
X86::CMOVG16rr, X86::CMOVGE16rr, X86::CMOVB16rr, X86::CMOVBE16rr,
- X86::CMOVA16rr, X86::CMOVAE16rr, X86::CMOVP16rr, X86::CMOVNP16rr,
+ X86::CMOVA16rr, X86::CMOVAE16rr, X86::CMOVP16rr, X86::CMOVNP16rr,
};
static const unsigned CMOVTAB32[] = {
X86::CMOVE32rr, X86::CMOVNE32rr, X86::CMOVL32rr, X86::CMOVLE32rr,
X86::CMOVG32rr, X86::CMOVGE32rr, X86::CMOVB32rr, X86::CMOVBE32rr,
- X86::CMOVA32rr, X86::CMOVAE32rr, X86::CMOVP32rr, X86::CMOVNP32rr,
+ X86::CMOVA32rr, X86::CMOVAE32rr, X86::CMOVP32rr, X86::CMOVNP32rr,
};
static const unsigned CMOVTABFP[] = {
X86::FCMOVE , X86::FCMOVNE, /*missing*/0, /*missing*/0,
/*missing*/0, /*missing*/0, X86::FCMOVB , X86::FCMOVBE,
X86::FCMOVA , X86::FCMOVAE, X86::FCMOVP , X86::FCMOVNP
};
-
- if (SetCCSDNode *SetCC = dyn_cast<SetCCSDNode>(Cond)) {
- if (MVT::isInteger(SetCC->getOperand(0).getValueType())) {
- switch (SetCC->getCondition()) {
+ static const int SSE_CMOVTAB[] = {
+ /*CMPEQ*/ 0, /*CMPNEQ*/ 4, /*missing*/ 0, /*missing*/ 0,
+ /*missing*/ 0, /*missing*/ 0, /*CMPLT*/ 1, /*CMPLE*/ 2,
+ /*CMPNLE*/ 6, /*CMPNLT*/ 5, /*CMPUNORD*/ 3, /*CMPORD*/ 7
+ };
+
+ if (Cond.getOpcode() == ISD::SETCC) {
+ ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
+ if (MVT::isInteger(Cond.getOperand(0).getValueType())) {
+ switch (CC) {
default: assert(0 && "Unknown integer comparison!");
case ISD::SETEQ: CondCode = EQ; break;
case ISD::SETGT: CondCode = GT; break;
// 1 | 0 | 0 | X == Y
// 1 | 1 | 1 | unordered
//
- switch (SetCC->getCondition()) {
+ switch (CC) {
default: assert(0 && "Unknown FP comparison!");
case ISD::SETUEQ:
case ISD::SETEQ: CondCode = EQ; break; // True if ZF = 1
break;
}
}
+
+
+ // There's no SSE equivalent of FCMOVE. For cases where we set a condition
+ // code above and one of the results of the select is +0.0, then we can fake
+ // it up through a clever AND with mask. Otherwise, we will fall through to
+ // the code below that will use a PHI node to select the right value.
+ if (X86ScalarSSE && (SVT == MVT::f32 || SVT == MVT::f64)) {
+ if (Cond.getOperand(0).getValueType() == SVT &&
+ NOT_SET != CondCode) {
+ ConstantFPSDNode *CT = dyn_cast<ConstantFPSDNode>(True);
+ ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(False);
+ bool TrueZero = CT && CT->isExactlyValue(0.0);
+ bool FalseZero = CF && CF->isExactlyValue(0.0);
+ if (TrueZero || FalseZero) {
+ SDOperand LHS = Cond.getOperand(0);
+ SDOperand RHS = Cond.getOperand(1);
+
+ // Select the two halves of the condition
+ unsigned RLHS, RRHS;
+ if (getRegPressure(LHS) > getRegPressure(RHS)) {
+ RLHS = SelectExpr(LHS);
+ RRHS = SelectExpr(RHS);
+ } else {
+ RRHS = SelectExpr(RHS);
+ RLHS = SelectExpr(LHS);
+ }
+
+ // Emit the comparison and generate a mask from it
+ unsigned MaskReg = MakeReg(SVT);
+ unsigned Opc = (SVT == MVT::f32) ? X86::CMPSSrr : X86::CMPSDrr;
+ BuildMI(BB, Opc, 3, MaskReg).addReg(RLHS).addReg(RRHS)
+ .addImm(SSE_CMOVTAB[CondCode]);
+
+ if (TrueZero) {
+ RFalse = SelectExpr(False);
+ Opc = (SVT == MVT::f32) ? X86::ANDNPSrr : X86::ANDNPDrr;
+ BuildMI(BB, Opc, 2, RDest).addReg(MaskReg).addReg(RFalse);
+ } else {
+ RTrue = SelectExpr(True);
+ Opc = (SVT == MVT::f32) ? X86::ANDPSrr : X86::ANDPDrr;
+ BuildMI(BB, Opc, 2, RDest).addReg(MaskReg).addReg(RTrue);
+ }
+ return;
+ }
+ }
+ }
+ }
+
+ // Select the true and false values for use in both the SSE PHI case, and the
+ // integer or x87 cmov cases below.
+ if (getRegPressure(True) > getRegPressure(False)) {
+ RTrue = SelectExpr(True);
+ RFalse = SelectExpr(False);
+ } else {
+ RFalse = SelectExpr(False);
+ RTrue = SelectExpr(True);
+ }
+
+ // Since there's no SSE equivalent of FCMOVE, and we couldn't generate an
+ // AND with mask, we'll have to do the normal RISC thing and generate a PHI
+ // node to select between the true and false values.
+ if (X86ScalarSSE && (SVT == MVT::f32 || SVT == MVT::f64)) {
+ // FIXME: emit a direct compare and branch rather than setting a cond reg
+ // and testing it.
+ unsigned CondReg = SelectExpr(Cond);
+ BuildMI(BB, X86::TEST8rr, 2).addReg(CondReg).addReg(CondReg);
+
+ // Create an iterator with which to insert the MBB for copying the false
+ // value and the MBB to hold the PHI instruction for this SetCC.
+ MachineBasicBlock *thisMBB = BB;
+ const BasicBlock *LLVM_BB = BB->getBasicBlock();
+ ilist<MachineBasicBlock>::iterator It = BB;
+ ++It;
+
+ // thisMBB:
+ // ...
+ // TrueVal = ...
+ // cmpTY ccX, r1, r2
+ // bCC sinkMBB
+ // fallthrough --> copy0MBB
+ MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
+ MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
+ BuildMI(BB, X86::JNE, 1).addMBB(sinkMBB);
+ MachineFunction *F = BB->getParent();
+ F->getBasicBlockList().insert(It, copy0MBB);
+ F->getBasicBlockList().insert(It, sinkMBB);
+ // Update machine-CFG edges
+ BB->addSuccessor(copy0MBB);
+ BB->addSuccessor(sinkMBB);
+
+ // copy0MBB:
+ // %FalseValue = ...
+ // # fallthrough to sinkMBB
+ BB = copy0MBB;
+ // Update machine-CFG edges
+ BB->addSuccessor(sinkMBB);
+
+ // sinkMBB:
+ // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
+ // ...
+ BB = sinkMBB;
+ BuildMI(BB, X86::PHI, 4, RDest).addReg(RFalse)
+ .addMBB(copy0MBB).addReg(RTrue).addMBB(thisMBB);
+ return;
}
unsigned Opc = 0;
return;
}
} else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(RHS)) {
- if (CN->isExactlyValue(+0.0) ||
- CN->isExactlyValue(-0.0)) {
+ if (!X86ScalarSSE && (CN->isExactlyValue(+0.0) ||
+ CN->isExactlyValue(-0.0))) {
unsigned Reg = SelectExpr(LHS);
BuildMI(BB, X86::FTST, 1).addReg(Reg);
BuildMI(BB, X86::FNSTSW8r, 0);
BuildMI(BB, X86::SAHF, 1);
+ return;
}
}
case MVT::i8: Opc = X86::CMP8rr; break;
case MVT::i16: Opc = X86::CMP16rr; break;
case MVT::i32: Opc = X86::CMP32rr; break;
- case MVT::f64: Opc = X86::FUCOMIr; break;
+ case MVT::f32: Opc = X86::UCOMISSrr; break;
+ case MVT::f64: Opc = X86ScalarSSE ? X86::UCOMISDrr : X86::FUCOMIr; break;
}
unsigned Tmp1, Tmp2;
if (getRegPressure(LHS) > getRegPressure(RHS)) {
/// isFoldableLoad - Return true if this is a load instruction that can safely
/// be folded into an operation that uses it.
-bool ISel::isFoldableLoad(SDOperand Op, SDOperand OtherOp) {
- if (Op.getOpcode() != ISD::LOAD ||
- // FIXME: currently can't fold constant pool indexes.
- isa<ConstantPoolSDNode>(Op.getOperand(1)))
+bool ISel::isFoldableLoad(SDOperand Op, SDOperand OtherOp, bool FloatPromoteOk){
+ if (Op.getOpcode() == ISD::LOAD) {
+ // FIXME: currently can't fold constant pool indexes.
+ if (isa<ConstantPoolSDNode>(Op.getOperand(1)))
+ return false;
+ } else if (FloatPromoteOk && Op.getOpcode() == ISD::EXTLOAD &&
+ cast<VTSDNode>(Op.getOperand(3))->getVT() == MVT::f32) {
+ // FIXME: currently can't fold constant pool indexes.
+ if (isa<ConstantPoolSDNode>(Op.getOperand(1)))
+ return false;
+ } else {
return false;
+ }
// If this load has already been emitted, we clearly can't fold it.
assert(Op.ResNo == 0 && "Not a use of the value of the load?");
return true;
}
}
-
+
return false;
}
unsigned ISel::SelectExpr(SDOperand N) {
unsigned Result;
- unsigned Tmp1, Tmp2, Tmp3;
- unsigned Opc = 0;
+ unsigned Tmp1 = 0, Tmp2 = 0, Tmp3 = 0, Opc = 0;
SDNode *Node = N.Val;
SDOperand Op0, Op1;
if (Node->getOpcode() == ISD::CopyFromReg) {
- // FIXME: Handle copy from physregs!
-
- // Just use the specified register as our input.
- return dyn_cast<RegSDNode>(Node)->getReg();
+ unsigned Reg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
+ // Just use the specified register as our input if we can.
+ if (MRegisterInfo::isVirtualRegister(Reg) || Reg == X86::ESP)
+ return Reg;
}
-
+
unsigned &Reg = ExprMap[N];
if (Reg) return Reg;
-
- if (N.getOpcode() != ISD::CALL && N.getOpcode() != ISD::ADD_PARTS &&
- N.getOpcode() != ISD::SUB_PARTS)
+
+ switch (N.getOpcode()) {
+ default:
Reg = Result = (N.getValueType() != MVT::Other) ?
- MakeReg(N.getValueType()) : 1;
- else {
+ MakeReg(N.getValueType()) : 1;
+ break;
+ case X86ISD::TAILCALL:
+ case X86ISD::CALL:
// If this is a call instruction, make sure to prepare ALL of the result
// values as well as the chain.
- if (N.getOpcode() == ISD::CALL) {
- if (Node->getNumValues() == 1)
- Reg = Result = 1; // Void call, just a chain.
- else {
- Result = MakeReg(Node->getValueType(0));
- ExprMap[N.getValue(0)] = Result;
- for (unsigned i = 1, e = N.Val->getNumValues()-1; i != e; ++i)
- ExprMap[N.getValue(i)] = MakeReg(Node->getValueType(i));
- ExprMap[SDOperand(Node, Node->getNumValues()-1)] = 1;
- }
- } else {
- Result = MakeReg(Node->getValueType(0));
- ExprMap[N.getValue(0)] = Result;
- for (unsigned i = 1, e = N.Val->getNumValues(); i != e; ++i)
+ ExprMap[N.getValue(0)] = 1;
+ if (Node->getNumValues() > 1) {
+ Result = MakeReg(Node->getValueType(1));
+ ExprMap[N.getValue(1)] = Result;
+ for (unsigned i = 2, e = Node->getNumValues(); i != e; ++i)
ExprMap[N.getValue(i)] = MakeReg(Node->getValueType(i));
+ } else {
+ Result = 1;
}
+ break;
+ case ISD::ADD_PARTS:
+ case ISD::SUB_PARTS:
+ case ISD::SHL_PARTS:
+ case ISD::SRL_PARTS:
+ case ISD::SRA_PARTS:
+ Result = MakeReg(Node->getValueType(0));
+ ExprMap[N.getValue(0)] = Result;
+ for (unsigned i = 1, e = N.Val->getNumValues(); i != e; ++i)
+ ExprMap[N.getValue(i)] = MakeReg(Node->getValueType(i));
+ break;
}
-
+
switch (N.getOpcode()) {
default:
Node->dump();
assert(0 && "Node not handled!\n");
+ case ISD::FP_EXTEND:
+ assert(X86ScalarSSE && "Scalar SSE FP must be enabled to use f32");
+ Tmp1 = SelectExpr(N.getOperand(0));
+ BuildMI(BB, X86::CVTSS2SDrr, 1, Result).addReg(Tmp1);
+ return Result;
+ case ISD::FP_ROUND:
+ assert(X86ScalarSSE && "Scalar SSE FP must be enabled to use f32");
+ Tmp1 = SelectExpr(N.getOperand(0));
+ BuildMI(BB, X86::CVTSD2SSrr, 1, Result).addReg(Tmp1);
+ return Result;
+ case ISD::CopyFromReg:
+ Select(N.getOperand(0));
+ if (Result == 1) {
+ Reg = Result = ExprMap[N.getValue(0)] =
+ MakeReg(N.getValue(0).getValueType());
+ }
+ Tmp1 = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
+ switch (Node->getValueType(0)) {
+ default: assert(0 && "Cannot CopyFromReg this!");
+ case MVT::i1:
+ case MVT::i8:
+ BuildMI(BB, X86::MOV8rr, 1, Result).addReg(Tmp1);
+ return Result;
+ case MVT::i16:
+ BuildMI(BB, X86::MOV16rr, 1, Result).addReg(Tmp1);
+ return Result;
+ case MVT::i32:
+ BuildMI(BB, X86::MOV32rr, 1, Result).addReg(Tmp1);
+ return Result;
+ }
+
case ISD::FrameIndex:
Tmp1 = cast<FrameIndexSDNode>(N)->getIndex();
addFrameReference(BuildMI(BB, X86::LEA32r, 4, Result), (int)Tmp1);
return Result;
case ISD::ConstantPool:
- Tmp1 = cast<ConstantPoolSDNode>(N)->getIndex();
+ Tmp1 = BB->getParent()->getConstantPool()->
+ getConstantPoolIndex(cast<ConstantPoolSDNode>(N)->get());
addConstantPoolReference(BuildMI(BB, X86::LEA32r, 4, Result), Tmp1);
return Result;
case ISD::ConstantFP:
+ if (X86ScalarSSE) {
+ assert(cast<ConstantFPSDNode>(N)->isExactlyValue(+0.0) &&
+ "SSE only supports +0.0");
+ Opc = (N.getValueType() == MVT::f32) ? X86::FLD0SS : X86::FLD0SD;
+ BuildMI(BB, Opc, 0, Result);
+ return Result;
+ }
ContainsFPCode = true;
Tmp1 = Result; // Intermediate Register
if (cast<ConstantFPSDNode>(N)->getValue() < 0.0 ||
}
BuildMI(BB, Opc, 1,Result).addImm(cast<ConstantSDNode>(N)->getValue());
return Result;
+ case ISD::UNDEF:
+ if (Node->getValueType(0) == MVT::f64) {
+ // FIXME: SHOULD TEACH STACKIFIER ABOUT UNDEF VALUES!
+ BuildMI(BB, X86::FLD0, 0, Result);
+ } else {
+ BuildMI(BB, X86::IMPLICIT_DEF, 0, Result);
+ }
+ return Result;
case ISD::GlobalAddress: {
GlobalValue *GV = cast<GlobalAddressSDNode>(N)->getGlobal();
- BuildMI(BB, X86::MOV32ri, 1, Result).addGlobalAddress(GV);
+ // For Darwin, external and weak symbols are indirect, so we want to load
+ // the value at address GV, not the value of GV itself.
+ if (Subtarget->getIndirectExternAndWeakGlobals() &&
+ (GV->hasWeakLinkage() || GV->isExternal())) {
+ BuildMI(BB, X86::MOV32rm, 4, Result).addReg(0).addZImm(1).addReg(0)
+ .addGlobalAddress(GV, false, 0);
+ } else {
+ BuildMI(BB, X86::MOV32ri, 1, Result).addGlobalAddress(GV);
+ }
return Result;
}
case ISD::ExternalSymbol: {
BuildMI(BB, X86::MOV32ri, 1, Result).addExternalSymbol(Sym);
return Result;
}
+ case ISD::ANY_EXTEND: // treat any extend like zext
case ISD::ZERO_EXTEND: {
int DestIs16 = N.getValueType() == MVT::i16;
int SrcIs16 = N.getOperand(0).getValueType() == MVT::i16;
X86AddressMode AM;
EmitFoldedLoad(N.getOperand(0), AM);
addFullAddress(BuildMI(BB, Opc[SrcIs16+DestIs16*2], 4, Result), AM);
-
+
return Result;
}
Tmp1 = SelectExpr(N.getOperand(0));
BuildMI(BB, Opc[SrcIs16+DestIs16*2], 1, Result).addReg(Tmp1);
return Result;
- }
+ }
case ISD::SIGN_EXTEND: {
int DestIs16 = N.getValueType() == MVT::i16;
int SrcIs16 = N.getOperand(0).getValueType() == MVT::i16;
BuildMI(BB, Opc, 1, Result).addReg(Tmp2);
return Result;
- case ISD::SINT_TO_FP:
- case ISD::UINT_TO_FP: {
- // FIXME: Most of this grunt work should be done by legalize!
- ContainsFPCode = true;
-
- // Promote the integer to a type supported by FLD. We do this because there
- // are no unsigned FLD instructions, so we must promote an unsigned value to
- // a larger signed value, then use FLD on the larger value.
- //
- MVT::ValueType PromoteType = MVT::Other;
- MVT::ValueType SrcTy = N.getOperand(0).getValueType();
+ case ISD::SINT_TO_FP: {
+ Tmp1 = SelectExpr(N.getOperand(0)); // Get the operand register
unsigned PromoteOpcode = 0;
- unsigned RealDestReg = Result;
- switch (SrcTy) {
- case MVT::i1:
- case MVT::i8:
- // We don't have the facilities for directly loading byte sized data from
- // memory (even signed). Promote it to 16 bits.
- PromoteType = MVT::i16;
- PromoteOpcode = Node->getOpcode() == ISD::SINT_TO_FP ?
- X86::MOVSX16rr8 : X86::MOVZX16rr8;
- break;
- case MVT::i16:
- if (Node->getOpcode() == ISD::UINT_TO_FP) {
- PromoteType = MVT::i32;
- PromoteOpcode = X86::MOVZX32rr16;
- }
- break;
- default:
- // Don't fild into the real destination.
- if (Node->getOpcode() == ISD::UINT_TO_FP)
- Result = MakeReg(Node->getValueType(0));
- break;
- }
- Tmp1 = SelectExpr(N.getOperand(0)); // Get the operand register
-
- if (PromoteType != MVT::Other) {
- Tmp2 = MakeReg(PromoteType);
- BuildMI(BB, PromoteOpcode, 1, Tmp2).addReg(Tmp1);
- SrcTy = PromoteType;
- Tmp1 = Tmp2;
+ // We can handle any sint to fp with the direct sse conversion instructions.
+ if (X86ScalarSSE) {
+ Opc = (N.getValueType() == MVT::f64) ? X86::CVTSI2SDrr : X86::CVTSI2SSrr;
+ BuildMI(BB, Opc, 1, Result).addReg(Tmp1);
+ return Result;
}
+ ContainsFPCode = true;
+
// Spill the integer to memory and reload it from there.
+ MVT::ValueType SrcTy = N.getOperand(0).getValueType();
unsigned Size = MVT::getSizeInBits(SrcTy)/8;
MachineFunction *F = BB->getParent();
int FrameIdx = F->getFrameInfo()->CreateStackObject(Size, Size);
switch (SrcTy) {
- case MVT::i64:
- assert(0 && "Cast ulong to FP not implemented yet!");
- // FIXME: this won't work for cast [u]long to FP
- addFrameReference(BuildMI(BB, X86::MOV32mr, 5),
- FrameIdx).addReg(Tmp1);
- addFrameReference(BuildMI(BB, X86::MOV32mr, 5),
- FrameIdx, 4).addReg(Tmp1+1);
- addFrameReference(BuildMI(BB, X86::FILD64m, 5, Result), FrameIdx);
- break;
case MVT::i32:
- addFrameReference(BuildMI(BB, X86::MOV32mr, 5),
- FrameIdx).addReg(Tmp1);
+ addFrameReference(BuildMI(BB, X86::MOV32mr, 5), FrameIdx).addReg(Tmp1);
addFrameReference(BuildMI(BB, X86::FILD32m, 5, Result), FrameIdx);
break;
case MVT::i16:
- addFrameReference(BuildMI(BB, X86::MOV16mr, 5),
- FrameIdx).addReg(Tmp1);
+ addFrameReference(BuildMI(BB, X86::MOV16mr, 5), FrameIdx).addReg(Tmp1);
addFrameReference(BuildMI(BB, X86::FILD16m, 5, Result), FrameIdx);
break;
default: break; // No promotion required.
}
-
- if (Node->getOpcode() == ISD::UINT_TO_FP && Result != RealDestReg) {
- // If this is a cast from uint -> double, we need to be careful when if
- // the "sign" bit is set. If so, we don't want to make a negative number,
- // we want to make a positive number. Emit code to add an offset if the
- // sign bit is set.
-
- // Compute whether the sign bit is set by shifting the reg right 31 bits.
- unsigned IsNeg = MakeReg(MVT::i32);
- BuildMI(BB, X86::SHR32ri, 2, IsNeg).addReg(Tmp1).addImm(31);
-
- // Create a CP value that has the offset in one word and 0 in the other.
- static ConstantInt *TheOffset = ConstantUInt::get(Type::ULongTy,
- 0x4f80000000000000ULL);
- unsigned CPI = F->getConstantPool()->getConstantPoolIndex(TheOffset);
- BuildMI(BB, X86::FADD32m, 5, RealDestReg).addReg(Result)
- .addConstantPoolIndex(CPI).addZImm(4).addReg(IsNeg).addSImm(0);
-
- } else if (Node->getOpcode() == ISD::UINT_TO_FP && SrcTy == MVT::i64) {
- // We need special handling for unsigned 64-bit integer sources. If the
- // input number has the "sign bit" set, then we loaded it incorrectly as a
- // negative 64-bit number. In this case, add an offset value.
-
- // Emit a test instruction to see if the dynamic input value was signed.
- BuildMI(BB, X86::TEST32rr, 2).addReg(Tmp1+1).addReg(Tmp1+1);
-
- // If the sign bit is set, get a pointer to an offset, otherwise get a
- // pointer to a zero.
- MachineConstantPool *CP = F->getConstantPool();
- unsigned Zero = MakeReg(MVT::i32);
- Constant *Null = Constant::getNullValue(Type::UIntTy);
- addConstantPoolReference(BuildMI(BB, X86::LEA32r, 5, Zero),
- CP->getConstantPoolIndex(Null));
- unsigned Offset = MakeReg(MVT::i32);
- Constant *OffsetCst = ConstantUInt::get(Type::UIntTy, 0x5f800000);
-
- addConstantPoolReference(BuildMI(BB, X86::LEA32r, 5, Offset),
- CP->getConstantPoolIndex(OffsetCst));
- unsigned Addr = MakeReg(MVT::i32);
- BuildMI(BB, X86::CMOVS32rr, 2, Addr).addReg(Zero).addReg(Offset);
-
- // Load the constant for an add. FIXME: this could make an 'fadd' that
- // reads directly from memory, but we don't support these yet.
- unsigned ConstReg = MakeReg(MVT::f64);
- addDirectMem(BuildMI(BB, X86::FLD32m, 4, ConstReg), Addr);
-
- BuildMI(BB, X86::FpADD, 2, RealDestReg).addReg(ConstReg).addReg(Result);
- }
- return RealDestReg;
+ return Result;
}
case ISD::FP_TO_SINT:
- case ISD::FP_TO_UINT: {
- // FIXME: Most of this grunt work should be done by legalize!
Tmp1 = SelectExpr(N.getOperand(0)); // Get the operand register
- // Change the floating point control register to use "round towards zero"
- // mode when truncating to an integer value.
- //
- MachineFunction *F = BB->getParent();
- int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2);
- addFrameReference(BuildMI(BB, X86::FNSTCW16m, 4), CWFrameIdx);
-
- // Load the old value of the high byte of the control word...
- unsigned HighPartOfCW = MakeReg(MVT::i8);
- addFrameReference(BuildMI(BB, X86::MOV8rm, 4, HighPartOfCW),
- CWFrameIdx, 1);
-
- // Set the high part to be round to zero...
- addFrameReference(BuildMI(BB, X86::MOV8mi, 5),
- CWFrameIdx, 1).addImm(12);
-
- // Reload the modified control word now...
- addFrameReference(BuildMI(BB, X86::FLDCW16m, 4), CWFrameIdx);
-
- // Restore the memory image of control word to original value
- addFrameReference(BuildMI(BB, X86::MOV8mr, 5),
- CWFrameIdx, 1).addReg(HighPartOfCW);
-
- // We don't have the facilities for directly storing byte sized data to
- // memory. Promote it to 16 bits. We also must promote unsigned values to
- // larger classes because we only have signed FP stores.
- MVT::ValueType StoreClass = Node->getValueType(0);
- if (StoreClass == MVT::i8 || Node->getOpcode() == ISD::FP_TO_UINT)
- switch (StoreClass) {
- case MVT::i8: StoreClass = MVT::i16; break;
- case MVT::i16: StoreClass = MVT::i32; break;
- case MVT::i32: StoreClass = MVT::i64; break;
- // The following treatment of cLong may not be perfectly right,
- // but it survives chains of casts of the form
- // double->ulong->double.
- case MVT::i64: StoreClass = MVT::i64; break;
- default: assert(0 && "Unknown store class!");
- }
-
- // Spill the integer to memory and reload it from there.
- unsigned Size = MVT::getSizeInBits(StoreClass)/8;
- int FrameIdx = F->getFrameInfo()->CreateStackObject(Size, Size);
-
- switch (StoreClass) {
- default: assert(0 && "Unknown store class!");
- case MVT::i16:
- addFrameReference(BuildMI(BB, X86::FIST16m, 5), FrameIdx).addReg(Tmp1);
- break;
- case MVT::i32:
- addFrameReference(BuildMI(BB, X86::FIST32m, 5), FrameIdx).addReg(Tmp1);
- break;
- case MVT::i64:
- addFrameReference(BuildMI(BB, X86::FISTP64m, 5), FrameIdx).addReg(Tmp1);
- break;
- }
-
- switch (Node->getValueType(0)) {
- default:
- assert(0 && "Unknown integer type!");
- case MVT::i64:
- // FIXME: this isn't gunna work.
- assert(0 && "Cast FP to long not implemented yet!");
- addFrameReference(BuildMI(BB, X86::MOV32rm, 4, Result), FrameIdx);
- addFrameReference(BuildMI(BB, X86::MOV32rm, 4, Result+1), FrameIdx, 4);
- case MVT::i32:
- addFrameReference(BuildMI(BB, X86::MOV32rm, 4, Result), FrameIdx);
- break;
- case MVT::i16:
- addFrameReference(BuildMI(BB, X86::MOV16rm, 4, Result), FrameIdx);
- break;
- case MVT::i8:
- addFrameReference(BuildMI(BB, X86::MOV8rm, 4, Result), FrameIdx);
- break;
+ // If the target supports SSE2 and is performing FP operations in SSE regs
+ // instead of the FP stack, then we can use the efficient CVTSS2SI and
+ // CVTSD2SI instructions.
+ assert(X86ScalarSSE);
+ if (MVT::f32 == N.getOperand(0).getValueType()) {
+ BuildMI(BB, X86::CVTTSS2SIrr, 1, Result).addReg(Tmp1);
+ } else if (MVT::f64 == N.getOperand(0).getValueType()) {
+ BuildMI(BB, X86::CVTTSD2SIrr, 1, Result).addReg(Tmp1);
+ } else {
+ assert(0 && "Not an f32 or f64?");
+ abort();
}
-
- // Reload the original control word now.
- addFrameReference(BuildMI(BB, X86::FLDCW16m, 4), CWFrameIdx);
return Result;
- }
+
+ case ISD::FADD:
case ISD::ADD:
Op0 = N.getOperand(0);
Op1 = N.getOperand(1);
- if (isFoldableLoad(Op0, Op1)) {
+ if (isFoldableLoad(Op0, Op1, true)) {
std::swap(Op0, Op1);
goto FoldAdd;
}
- if (isFoldableLoad(Op1, Op0)) {
+ if (isFoldableLoad(Op1, Op0, true)) {
FoldAdd:
switch (N.getValueType()) {
default: assert(0 && "Cannot add this type!");
case MVT::i8: Opc = X86::ADD8rm; break;
case MVT::i16: Opc = X86::ADD16rm; break;
case MVT::i32: Opc = X86::ADD32rm; break;
- case MVT::f32: Opc = X86::FADD32m; break;
- case MVT::f64: Opc = X86::FADD64m; break;
+ case MVT::f32: Opc = X86::ADDSSrm; break;
+ case MVT::f64:
+ // For F64, handle promoted load operations (from F32) as well!
+ if (X86ScalarSSE) {
+ assert(Op1.getOpcode() == ISD::LOAD && "SSE load not promoted");
+ Opc = X86::ADDSDrm;
+ } else {
+ Opc = Op1.getOpcode() == ISD::LOAD ? X86::FADD64m : X86::FADD32m;
+ }
+ break;
}
X86AddressMode AM;
EmitFoldedLoad(Op1, AM);
case MVT::i8: Opc = X86::ADD8rr; break;
case MVT::i16: Opc = X86::ADD16rr; break;
case MVT::i32: Opc = X86::ADD32rr; break;
- case MVT::f64: Opc = X86::FpADD; break;
+ case MVT::f32: Opc = X86::ADDSSrr; break;
+ case MVT::f64: Opc = X86ScalarSSE ? X86::ADDSDrr : X86::FpADD; break;
}
if (getRegPressure(Op0) > getRegPressure(Op1)) {
BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
return Result;
+
+ case ISD::FSQRT:
+ Tmp1 = SelectExpr(Node->getOperand(0));
+ if (X86ScalarSSE) {
+ Opc = (N.getValueType() == MVT::f32) ? X86::SQRTSSrr : X86::SQRTSDrr;
+ BuildMI(BB, Opc, 1, Result).addReg(Tmp1);
+ } else {
+ BuildMI(BB, X86::FSQRT, 1, Result).addReg(Tmp1);
+ }
+ return Result;
+
+ // FIXME:
+ // Once we can spill 16 byte constants into the constant pool, we can
+ // implement SSE equivalents of FABS and FCHS.
+ case ISD::FABS:
+ case ISD::FNEG:
+ case ISD::FSIN:
+ case ISD::FCOS:
+ assert(N.getValueType()==MVT::f64 && "Illegal type for this operation");
+ Tmp1 = SelectExpr(Node->getOperand(0));
+ switch (N.getOpcode()) {
+ default: assert(0 && "Unreachable!");
+ case ISD::FABS: BuildMI(BB, X86::FABS, 1, Result).addReg(Tmp1); break;
+ case ISD::FNEG: BuildMI(BB, X86::FCHS, 1, Result).addReg(Tmp1); break;
+ case ISD::FSIN: BuildMI(BB, X86::FSIN, 1, Result).addReg(Tmp1); break;
+ case ISD::FCOS: BuildMI(BB, X86::FCOS, 1, Result).addReg(Tmp1); break;
+ }
+ return Result;
+
+ case ISD::MULHU:
+ switch (N.getValueType()) {
+ default: assert(0 && "Unsupported VT!");
+ case MVT::i8: Tmp2 = X86::MUL8r; break;
+ case MVT::i16: Tmp2 = X86::MUL16r; break;
+ case MVT::i32: Tmp2 = X86::MUL32r; break;
+ }
+ // FALL THROUGH
+ case ISD::MULHS: {
+ unsigned MovOpc, LowReg, HiReg;
+ switch (N.getValueType()) {
+ default: assert(0 && "Unsupported VT!");
+ case MVT::i8:
+ MovOpc = X86::MOV8rr;
+ LowReg = X86::AL;
+ HiReg = X86::AH;
+ Opc = X86::IMUL8r;
+ break;
+ case MVT::i16:
+ MovOpc = X86::MOV16rr;
+ LowReg = X86::AX;
+ HiReg = X86::DX;
+ Opc = X86::IMUL16r;
+ break;
+ case MVT::i32:
+ MovOpc = X86::MOV32rr;
+ LowReg = X86::EAX;
+ HiReg = X86::EDX;
+ Opc = X86::IMUL32r;
+ break;
+ }
+ if (Node->getOpcode() != ISD::MULHS)
+ Opc = Tmp2; // Get the MULHU opcode.
+
+ Op0 = Node->getOperand(0);
+ Op1 = Node->getOperand(1);
+ if (getRegPressure(Op0) > getRegPressure(Op1)) {
+ Tmp1 = SelectExpr(Op0);
+ Tmp2 = SelectExpr(Op1);
+ } else {
+ Tmp2 = SelectExpr(Op1);
+ Tmp1 = SelectExpr(Op0);
+ }
+
+ // FIXME: Implement folding of loads into the memory operands here!
+ BuildMI(BB, MovOpc, 1, LowReg).addReg(Tmp1);
+ BuildMI(BB, Opc, 1).addReg(Tmp2);
+ BuildMI(BB, MovOpc, 1, Result).addReg(HiReg);
+ return Result;
+ }
+
+ case ISD::FSUB:
+ case ISD::FMUL:
case ISD::SUB:
case ISD::MUL:
case ISD::AND:
X86::SUB8rm, X86::SUB16rm, X86::SUB32rm, X86::FSUB32m, X86::FSUB64m,
X86::SUB8rr, X86::SUB16rr, X86::SUB32rr, X86::FpSUB , X86::FpSUB,
};
+ static const unsigned SSE_SUBTab[] = {
+ X86::SUB8ri, X86::SUB16ri, X86::SUB32ri, 0, 0,
+ X86::SUB8rm, X86::SUB16rm, X86::SUB32rm, X86::SUBSSrm, X86::SUBSDrm,
+ X86::SUB8rr, X86::SUB16rr, X86::SUB32rr, X86::SUBSSrr, X86::SUBSDrr,
+ };
static const unsigned MULTab[] = {
0, X86::IMUL16rri, X86::IMUL32rri, 0, 0,
0, X86::IMUL16rm , X86::IMUL32rm, X86::FMUL32m, X86::FMUL64m,
0, X86::IMUL16rr , X86::IMUL32rr, X86::FpMUL , X86::FpMUL,
};
+ static const unsigned SSE_MULTab[] = {
+ 0, X86::IMUL16rri, X86::IMUL32rri, 0, 0,
+ 0, X86::IMUL16rm , X86::IMUL32rm, X86::MULSSrm, X86::MULSDrm,
+ 0, X86::IMUL16rr , X86::IMUL32rr, X86::MULSSrr, X86::MULSDrr,
+ };
static const unsigned ANDTab[] = {
X86::AND8ri, X86::AND16ri, X86::AND32ri, 0, 0,
X86::AND8rm, X86::AND16rm, X86::AND32rm, 0, 0,
- X86::AND8rr, X86::AND16rr, X86::AND32rr, 0, 0,
+ X86::AND8rr, X86::AND16rr, X86::AND32rr, 0, 0,
};
static const unsigned ORTab[] = {
X86::OR8ri, X86::OR16ri, X86::OR32ri, 0, 0,
}
switch (Node->getOpcode()) {
default: assert(0 && "Unreachable!");
- case ISD::SUB: Opc = SUBTab[Opc]; break;
- case ISD::MUL: Opc = MULTab[Opc]; break;
+ case ISD::FSUB:
+ case ISD::SUB: Opc = X86ScalarSSE ? SSE_SUBTab[Opc] : SUBTab[Opc]; break;
+ case ISD::FMUL:
+ case ISD::MUL: Opc = X86ScalarSSE ? SSE_MULTab[Opc] : MULTab[Opc]; break;
case ISD::AND: Opc = ANDTab[Opc]; break;
case ISD::OR: Opc = ORTab[Opc]; break;
case ISD::XOR: Opc = XORTab[Opc]; break;
}
}
- if (isFoldableLoad(Op0, Op1))
- if (Node->getOpcode() != ISD::SUB) {
+ if (isFoldableLoad(Op0, Op1, true))
+ if (Node->getOpcode() != ISD::SUB && Node->getOpcode() != ISD::FSUB) {
std::swap(Op0, Op1);
goto FoldOps;
} else {
- // Emit 'reverse' subract, with a memory operand.
- switch (N.getValueType()) {
- default: Opc = 0; break;
- case MVT::f32: Opc = X86::FSUBR32m; break;
- case MVT::f64: Opc = X86::FSUBR64m; break;
- }
- if (Opc) {
+ // For FP, emit 'reverse' subract, with a memory operand.
+ if (N.getValueType() == MVT::f64 && !X86ScalarSSE) {
+ if (Op0.getOpcode() == ISD::EXTLOAD)
+ Opc = X86::FSUBR32m;
+ else
+ Opc = X86::FSUBR64m;
+
X86AddressMode AM;
EmitFoldedLoad(Op0, AM);
Tmp1 = SelectExpr(Op1);
}
}
- if (isFoldableLoad(Op1, Op0)) {
+ if (isFoldableLoad(Op1, Op0, true)) {
FoldOps:
switch (N.getValueType()) {
default: assert(0 && "Cannot operate on this type!");
case MVT::i16: Opc = 6; break;
case MVT::i32: Opc = 7; break;
case MVT::f32: Opc = 8; break;
- case MVT::f64: Opc = 9; break;
+ // For F64, handle promoted load operations (from F32) as well!
+ case MVT::f64:
+ assert((!X86ScalarSSE || Op1.getOpcode() == ISD::LOAD) &&
+ "SSE load should have been promoted");
+ Opc = Op1.getOpcode() == ISD::LOAD ? 9 : 8; break;
}
switch (Node->getOpcode()) {
default: assert(0 && "Unreachable!");
- case ISD::SUB: Opc = SUBTab[Opc]; break;
- case ISD::MUL: Opc = MULTab[Opc]; break;
+ case ISD::FSUB:
+ case ISD::SUB: Opc = X86ScalarSSE ? SSE_SUBTab[Opc] : SUBTab[Opc]; break;
+ case ISD::FMUL:
+ case ISD::MUL: Opc = X86ScalarSSE ? SSE_MULTab[Opc] : MULTab[Opc]; break;
case ISD::AND: Opc = ANDTab[Opc]; break;
case ISD::OR: Opc = ORTab[Opc]; break;
case ISD::XOR: Opc = XORTab[Opc]; break;
}
switch (Node->getOpcode()) {
default: assert(0 && "Unreachable!");
- case ISD::SUB: Opc = SUBTab[Opc]; break;
- case ISD::MUL: Opc = MULTab[Opc]; break;
+ case ISD::FSUB:
+ case ISD::SUB: Opc = X86ScalarSSE ? SSE_SUBTab[Opc] : SUBTab[Opc]; break;
+ case ISD::FMUL:
+ case ISD::MUL: Opc = X86ScalarSSE ? SSE_MULTab[Opc] : MULTab[Opc]; break;
case ISD::AND: Opc = ANDTab[Opc]; break;
case ISD::OR: Opc = ORTab[Opc]; break;
case ISD::XOR: Opc = XORTab[Opc]; break;
return Result+N.ResNo;
}
- case ISD::SELECT:
- if (getRegPressure(N.getOperand(1)) > getRegPressure(N.getOperand(2))) {
- Tmp2 = SelectExpr(N.getOperand(1));
- Tmp3 = SelectExpr(N.getOperand(2));
+ case ISD::SHL_PARTS:
+ case ISD::SRA_PARTS:
+ case ISD::SRL_PARTS: {
+ assert(N.getNumOperands() == 3 && N.getValueType() == MVT::i32 &&
+ "Not an i64 shift!");
+ unsigned ShiftOpLo = SelectExpr(N.getOperand(0));
+ unsigned ShiftOpHi = SelectExpr(N.getOperand(1));
+ unsigned TmpReg = MakeReg(MVT::i32);
+ if (N.getOpcode() == ISD::SRA_PARTS) {
+ // If this is a SHR of a Long, then we need to do funny sign extension
+ // stuff. TmpReg gets the value to use as the high-part if we are
+ // shifting more than 32 bits.
+ BuildMI(BB, X86::SAR32ri, 2, TmpReg).addReg(ShiftOpHi).addImm(31);
} else {
- Tmp3 = SelectExpr(N.getOperand(2));
- Tmp2 = SelectExpr(N.getOperand(1));
+ // Other shifts use a fixed zero value if the shift is more than 32 bits.
+ BuildMI(BB, X86::MOV32ri, 1, TmpReg).addImm(0);
+ }
+
+ // Initialize CL with the shift amount.
+ unsigned ShiftAmountReg = SelectExpr(N.getOperand(2));
+ BuildMI(BB, X86::MOV8rr, 1, X86::CL).addReg(ShiftAmountReg);
+
+ unsigned TmpReg2 = MakeReg(MVT::i32);
+ unsigned TmpReg3 = MakeReg(MVT::i32);
+ if (N.getOpcode() == ISD::SHL_PARTS) {
+ // TmpReg2 = shld inHi, inLo
+ BuildMI(BB, X86::SHLD32rrCL, 2,TmpReg2).addReg(ShiftOpHi)
+ .addReg(ShiftOpLo);
+ // TmpReg3 = shl inLo, CL
+ BuildMI(BB, X86::SHL32rCL, 1, TmpReg3).addReg(ShiftOpLo);
+
+ // Set the flags to indicate whether the shift was by more than 32 bits.
+ BuildMI(BB, X86::TEST8ri, 2).addReg(X86::CL).addImm(32);
+
+ // DestHi = (>32) ? TmpReg3 : TmpReg2;
+ BuildMI(BB, X86::CMOVNE32rr, 2,
+ Result+1).addReg(TmpReg2).addReg(TmpReg3);
+ // DestLo = (>32) ? TmpReg : TmpReg3;
+ BuildMI(BB, X86::CMOVNE32rr, 2,
+ Result).addReg(TmpReg3).addReg(TmpReg);
+ } else {
+ // TmpReg2 = shrd inLo, inHi
+ BuildMI(BB, X86::SHRD32rrCL,2,TmpReg2).addReg(ShiftOpLo)
+ .addReg(ShiftOpHi);
+ // TmpReg3 = s[ah]r inHi, CL
+ BuildMI(BB, N.getOpcode() == ISD::SRA_PARTS ? X86::SAR32rCL
+ : X86::SHR32rCL, 1, TmpReg3)
+ .addReg(ShiftOpHi);
+
+ // Set the flags to indicate whether the shift was by more than 32 bits.
+ BuildMI(BB, X86::TEST8ri, 2).addReg(X86::CL).addImm(32);
+
+ // DestLo = (>32) ? TmpReg3 : TmpReg2;
+ BuildMI(BB, X86::CMOVNE32rr, 2,
+ Result).addReg(TmpReg2).addReg(TmpReg3);
+
+ // DestHi = (>32) ? TmpReg : TmpReg3;
+ BuildMI(BB, X86::CMOVNE32rr, 2,
+ Result+1).addReg(TmpReg3).addReg(TmpReg);
}
- EmitSelectCC(N.getOperand(0), N.getValueType(), Tmp2, Tmp3, Result);
+ return Result+N.ResNo;
+ }
+
+ case ISD::SELECT:
+ EmitSelectCC(N.getOperand(0), N.getOperand(1), N.getOperand(2),
+ N.getValueType(), Result);
return Result;
+ case ISD::FDIV:
+ case ISD::FREM:
case ISD::SDIV:
case ISD::UDIV:
case ISD::SREM:
assert((N.getOpcode() != ISD::SREM || MVT::isInteger(N.getValueType())) &&
"We don't support this operator!");
- if (N.getOpcode() == ISD::SDIV)
+ if (N.getOpcode() == ISD::SDIV || N.getOpcode() == ISD::FDIV) {
+ // We can fold loads into FpDIVs, but not really into any others.
+ if (N.getValueType() == MVT::f64 && !X86ScalarSSE) {
+ // Check for reversed and unreversed DIV.
+ if (isFoldableLoad(N.getOperand(0), N.getOperand(1), true)) {
+ if (N.getOperand(0).getOpcode() == ISD::EXTLOAD)
+ Opc = X86::FDIVR32m;
+ else
+ Opc = X86::FDIVR64m;
+ X86AddressMode AM;
+ EmitFoldedLoad(N.getOperand(0), AM);
+ Tmp1 = SelectExpr(N.getOperand(1));
+ addFullAddress(BuildMI(BB, Opc, 5, Result).addReg(Tmp1), AM);
+ return Result;
+ } else if (isFoldableLoad(N.getOperand(1), N.getOperand(0), true) &&
+ N.getOperand(1).getOpcode() == ISD::LOAD) {
+ if (N.getOperand(1).getOpcode() == ISD::EXTLOAD)
+ Opc = X86::FDIV32m;
+ else
+ Opc = X86::FDIV64m;
+ X86AddressMode AM;
+ EmitFoldedLoad(N.getOperand(1), AM);
+ Tmp1 = SelectExpr(N.getOperand(0));
+ addFullAddress(BuildMI(BB, Opc, 5, Result).addReg(Tmp1), AM);
+ return Result;
+ }
+ }
+
if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
// FIXME: These special cases should be handled by the lowering impl!
unsigned RHS = CN->getValue();
RHS = -RHS;
}
if (RHS && (RHS & (RHS-1)) == 0) { // Signed division by power of 2?
- unsigned Log = log2(RHS);
- unsigned TmpReg = MakeReg(N.getValueType());
+ unsigned Log = Log2_32(RHS);
unsigned SAROpc, SHROpc, ADDOpc, NEGOpc;
switch (N.getValueType()) {
default: assert("Unknown type to signed divide!");
NEGOpc = X86::NEG32r;
break;
}
+ unsigned RegSize = MVT::getSizeInBits(N.getValueType());
Tmp1 = SelectExpr(N.getOperand(0));
- BuildMI(BB, SAROpc, 2, TmpReg).addReg(Tmp1).addImm(Log-1);
+ unsigned TmpReg;
+ if (Log != 1) {
+ TmpReg = MakeReg(N.getValueType());
+ BuildMI(BB, SAROpc, 2, TmpReg).addReg(Tmp1).addImm(Log-1);
+ } else {
+ TmpReg = Tmp1;
+ }
unsigned TmpReg2 = MakeReg(N.getValueType());
- BuildMI(BB, SHROpc, 2, TmpReg2).addReg(TmpReg).addImm(32-Log);
+ BuildMI(BB, SHROpc, 2, TmpReg2).addReg(TmpReg).addImm(RegSize-Log);
unsigned TmpReg3 = MakeReg(N.getValueType());
BuildMI(BB, ADDOpc, 2, TmpReg3).addReg(Tmp1).addReg(TmpReg2);
-
+
unsigned TmpReg4 = isNeg ? MakeReg(N.getValueType()) : Result;
BuildMI(BB, SAROpc, 2, TmpReg4).addReg(TmpReg3).addImm(Log);
if (isNeg)
return Result;
}
}
+ }
if (getRegPressure(N.getOperand(0)) > getRegPressure(N.getOperand(1))) {
Tmp1 = SelectExpr(N.getOperand(0));
ClrOpcode = X86::MOV32ri;
SExtOpcode = X86::CDQ;
break;
+ case MVT::f32:
+ BuildMI(BB, X86::DIVSSrr, 2, Result).addReg(Tmp1).addReg(Tmp2);
+ return Result;
case MVT::f64:
- BuildMI(BB, X86::FpDIV, 2, Result).addReg(Tmp1).addReg(Tmp2);
+ Opc = X86ScalarSSE ? X86::DIVSDrr : X86::FpDIV;
+ BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
return Result;
}
}
// Emit the DIV/IDIV instruction.
- BuildMI(BB, DivOpcode, 1).addReg(Tmp2);
+ BuildMI(BB, DivOpcode, 1).addReg(Tmp2);
// Get the result of the divide or rem.
BuildMI(BB, MovOpcode, 1, Result).addReg(isDiv ? LoReg : HiReg);
BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp1);
return Result;
}
-
+
switch (N.getValueType()) {
default: assert(0 && "Cannot shift this type!");
case MVT::i8: Opc = X86::SHL8ri; break;
case MVT::i32: Opc = X86::SHL32rCL; break;
}
BuildMI(BB, X86::MOV8rr, 1, X86::CL).addReg(Tmp2);
- BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
+ BuildMI(BB, Opc, 1, Result).addReg(Tmp1);
return Result;
case ISD::SRL:
if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
case MVT::i32: Opc = X86::SHR32rCL; break;
}
BuildMI(BB, X86::MOV8rr, 1, X86::CL).addReg(Tmp2);
- BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
+ BuildMI(BB, Opc, 1, Result).addReg(Tmp1);
return Result;
case ISD::SRA:
if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
case MVT::i32: Opc = X86::SAR32rCL; break;
}
BuildMI(BB, X86::MOV8rr, 1, X86::CL).addReg(Tmp2);
- BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
+ BuildMI(BB, Opc, 1, Result).addReg(Tmp1);
return Result;
case ISD::SETCC:
EmitCMP(N.getOperand(0), N.getOperand(1), Node->hasOneUse());
- EmitSetCC(BB, Result, cast<SetCCSDNode>(N)->getCondition(),
+ EmitSetCC(BB, Result, cast<CondCodeSDNode>(N.getOperand(2))->get(),
MVT::isFloatingPoint(N.getOperand(1).getValueType()));
return Result;
case ISD::LOAD:
case MVT::i8: Opc = X86::MOV8rm; break;
case MVT::i16: Opc = X86::MOV16rm; break;
case MVT::i32: Opc = X86::MOV32rm; break;
- case MVT::f64: Opc = X86::FLD64m; ContainsFPCode = true; break;
+ case MVT::f32: Opc = X86::MOVSSrm; break;
+ case MVT::f64:
+ if (X86ScalarSSE) {
+ Opc = X86::MOVSDrm;
+ } else {
+ Opc = X86::FLD64m;
+ ContainsFPCode = true;
+ }
+ break;
+ }
+
+ if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N.getOperand(1))){
+ unsigned CPIdx = BB->getParent()->getConstantPool()->
+ getConstantPoolIndex(CP->get());
+ Select(N.getOperand(0));
+ addConstantPoolReference(BuildMI(BB, Opc, 4, Result), CPIdx);
+ } else {
+ X86AddressMode AM;
+
+ SDOperand Chain = N.getOperand(0);
+ SDOperand Address = N.getOperand(1);
+ if (getRegPressure(Chain) > getRegPressure(Address)) {
+ Select(Chain);
+ SelectAddress(Address, AM);
+ } else {
+ SelectAddress(Address, AM);
+ Select(Chain);
+ }
+
+ addFullAddress(BuildMI(BB, Opc, 4, Result), AM);
}
+ return Result;
+ case X86ISD::FILD64m:
+ // Make sure we generate both values.
+ assert(Result != 1 && N.getValueType() == MVT::f64);
+ if (!ExprMap.insert(std::make_pair(N.getValue(1), 1)).second)
+ assert(0 && "Load already emitted!?");
- if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N.getOperand(1))){
- Select(N.getOperand(0));
- addConstantPoolReference(BuildMI(BB, Opc, 4, Result), CP->getIndex());
- } else {
+ {
X86AddressMode AM;
SDOperand Chain = N.getOperand(0);
Select(Chain);
}
- addFullAddress(BuildMI(BB, Opc, 4, Result), AM);
+ addFullAddress(BuildMI(BB, X86::FILD64m, 4, Result), AM);
}
return Result;
if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N.getOperand(1)))
if (Node->getValueType(0) == MVT::f64) {
- assert(cast<MVTSDNode>(Node)->getExtraValueType() == MVT::f32 &&
+ assert(cast<VTSDNode>(Node->getOperand(3))->getVT() == MVT::f32 &&
"Bad EXTLOAD!");
- addConstantPoolReference(BuildMI(BB, X86::FLD32m, 4, Result),
- CP->getIndex());
+ unsigned CPIdx = BB->getParent()->getConstantPool()->
+ getConstantPoolIndex(CP->get());
+
+ addConstantPoolReference(BuildMI(BB, X86::FLD32m, 4, Result), CPIdx);
return Result;
}
switch (Node->getValueType(0)) {
default: assert(0 && "Unknown type to sign extend to.");
case MVT::f64:
- assert(cast<MVTSDNode>(Node)->getExtraValueType() == MVT::f32 &&
+ assert(cast<VTSDNode>(Node->getOperand(3))->getVT() == MVT::f32 &&
"Bad EXTLOAD!");
addFullAddress(BuildMI(BB, X86::FLD32m, 5, Result), AM);
break;
case MVT::i32:
- switch (cast<MVTSDNode>(Node)->getExtraValueType()) {
+ switch (cast<VTSDNode>(Node->getOperand(3))->getVT()) {
default:
assert(0 && "Bad zero extend!");
case MVT::i1:
}
break;
case MVT::i16:
- assert(cast<MVTSDNode>(Node)->getExtraValueType() <= MVT::i8 &&
+ assert(cast<VTSDNode>(Node->getOperand(3))->getVT() <= MVT::i8 &&
"Bad zero extend!");
addFullAddress(BuildMI(BB, X86::MOVSX16rm8, 5, Result), AM);
break;
case MVT::i8:
- assert(cast<MVTSDNode>(Node)->getExtraValueType() == MVT::i1 &&
+ assert(cast<VTSDNode>(Node->getOperand(3))->getVT() == MVT::i1 &&
"Bad zero extend!");
addFullAddress(BuildMI(BB, X86::MOV8rm, 5, Result), AM);
break;
case MVT::i8: assert(0 && "Cannot sign extend from bool!");
default: assert(0 && "Unknown type to sign extend to.");
case MVT::i32:
- switch (cast<MVTSDNode>(Node)->getExtraValueType()) {
+ switch (cast<VTSDNode>(Node->getOperand(3))->getVT()) {
default:
case MVT::i1: assert(0 && "Cannot sign extend from bool!");
case MVT::i8:
}
break;
case MVT::i16:
- assert(cast<MVTSDNode>(Node)->getExtraValueType() == MVT::i8 &&
+ assert(cast<VTSDNode>(Node->getOperand(3))->getVT() == MVT::i8 &&
"Cannot sign extend from bool!");
addFullAddress(BuildMI(BB, X86::MOVSX16rm8, 5, Result), AM);
break;
<< " the stack alignment yet!";
abort();
}
-
+
if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
Select(N.getOperand(0));
BuildMI(BB, X86::SUB32ri, 2, X86::ESP).addReg(X86::ESP)
BuildMI(BB, X86::MOV32rr, 1, Result).addReg(X86::ESP);
return Result;
- case ISD::CALL:
+ case X86ISD::TAILCALL:
+ case X86ISD::CALL: {
// The chain for this call is now lowered.
- ExprMap.insert(std::make_pair(N.getValue(Node->getNumValues()-1), 1));
+ ExprMap.insert(std::make_pair(N.getValue(0), 1));
+
+ bool isDirect = isa<GlobalAddressSDNode>(N.getOperand(1)) ||
+ isa<ExternalSymbolSDNode>(N.getOperand(1));
+ unsigned Callee = 0;
+ if (isDirect) {
+ Select(N.getOperand(0));
+ } else {
+ if (getRegPressure(N.getOperand(0)) > getRegPressure(N.getOperand(1))) {
+ Select(N.getOperand(0));
+ Callee = SelectExpr(N.getOperand(1));
+ } else {
+ Callee = SelectExpr(N.getOperand(1));
+ Select(N.getOperand(0));
+ }
+ }
+
+ // If this call has values to pass in registers, do so now.
+ if (Node->getNumOperands() > 4) {
+ // The first value is passed in (a part of) EAX, the second in EDX.
+ unsigned RegOp1 = SelectExpr(N.getOperand(4));
+ unsigned RegOp2 =
+ Node->getNumOperands() > 5 ? SelectExpr(N.getOperand(5)) : 0;
+
+ switch (N.getOperand(4).getValueType()) {
+ default: assert(0 && "Bad thing to pass in regs");
+ case MVT::i1:
+ case MVT::i8: BuildMI(BB, X86::MOV8rr , 1,X86::AL).addReg(RegOp1); break;
+ case MVT::i16: BuildMI(BB, X86::MOV16rr, 1,X86::AX).addReg(RegOp1); break;
+ case MVT::i32: BuildMI(BB, X86::MOV32rr, 1,X86::EAX).addReg(RegOp1);break;
+ }
+ if (RegOp2)
+ switch (N.getOperand(5).getValueType()) {
+ default: assert(0 && "Bad thing to pass in regs");
+ case MVT::i1:
+ case MVT::i8:
+ BuildMI(BB, X86::MOV8rr , 1, X86::DL).addReg(RegOp2);
+ break;
+ case MVT::i16:
+ BuildMI(BB, X86::MOV16rr, 1, X86::DX).addReg(RegOp2);
+ break;
+ case MVT::i32:
+ BuildMI(BB, X86::MOV32rr, 1, X86::EDX).addReg(RegOp2);
+ break;
+ }
+ }
if (GlobalAddressSDNode *GASD =
dyn_cast<GlobalAddressSDNode>(N.getOperand(1))) {
- Select(N.getOperand(0));
BuildMI(BB, X86::CALLpcrel32, 1).addGlobalAddress(GASD->getGlobal(),true);
} else if (ExternalSymbolSDNode *ESSDN =
dyn_cast<ExternalSymbolSDNode>(N.getOperand(1))) {
- Select(N.getOperand(0));
BuildMI(BB, X86::CALLpcrel32,
1).addExternalSymbol(ESSDN->getSymbol(), true);
} else {
BuildMI(BB, X86::CALL32r, 1).addReg(Tmp1);
}
+
+ // Get caller stack amount and amount the callee added to the stack pointer.
+ Tmp1 = cast<ConstantSDNode>(N.getOperand(2))->getValue();
+ Tmp2 = cast<ConstantSDNode>(N.getOperand(3))->getValue();
+ BuildMI(BB, X86::ADJCALLSTACKUP, 2).addImm(Tmp1).addImm(Tmp2);
+
+ if (Node->getNumValues() != 1)
+ switch (Node->getValueType(1)) {
+ default: assert(0 && "Unknown value type for call result!");
+ case MVT::Other: return 1;
+ case MVT::i1:
+ case MVT::i8:
+ BuildMI(BB, X86::MOV8rr, 1, Result).addReg(X86::AL);
+ break;
+ case MVT::i16:
+ BuildMI(BB, X86::MOV16rr, 1, Result).addReg(X86::AX);
+ break;
+ case MVT::i32:
+ BuildMI(BB, X86::MOV32rr, 1, Result).addReg(X86::EAX);
+ if (Node->getNumValues() == 3 && Node->getValueType(2) == MVT::i32)
+ BuildMI(BB, X86::MOV32rr, 1, Result+1).addReg(X86::EDX);
+ break;
+ case MVT::f64: // Floating-point return values live in %ST(0)
+ if (X86ScalarSSE) {
+ ContainsFPCode = true;
+ BuildMI(BB, X86::FpGETRESULT, 1, X86::FP0);
+
+ unsigned Size = MVT::getSizeInBits(MVT::f64)/8;
+ MachineFunction *F = BB->getParent();
+ int FrameIdx = F->getFrameInfo()->CreateStackObject(Size, Size);
+ addFrameReference(BuildMI(BB, X86::FST64m, 5), FrameIdx).addReg(X86::FP0);
+ addFrameReference(BuildMI(BB, X86::MOVSDrm, 4, Result), FrameIdx);
+ break;
+ } else {
+ ContainsFPCode = true;
+ BuildMI(BB, X86::FpGETRESULT, 1, Result);
+ break;
+ }
+ }
+ return Result+N.ResNo-1;
+ }
+ case ISD::READPORT:
+ // First, determine that the size of the operand falls within the acceptable
+ // range for this architecture.
+ //
+ if (Node->getOperand(1).getValueType() != MVT::i16) {
+ std::cerr << "llvm.readport: Address size is not 16 bits\n";
+ exit(1);
+ }
+
+ // Make sure we generate both values.
+ if (Result != 1) { // Generate the token
+ if (!ExprMap.insert(std::make_pair(N.getValue(1), 1)).second)
+ assert(0 && "readport already emitted!?");
+ } else
+ Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType());
+
+ Select(Node->getOperand(0)); // Select the chain.
+
+ // If the port is a single-byte constant, use the immediate form.
+ if (ConstantSDNode *Port = dyn_cast<ConstantSDNode>(Node->getOperand(1)))
+ if ((Port->getValue() & 255) == Port->getValue()) {
+ switch (Node->getValueType(0)) {
+ case MVT::i8:
+ BuildMI(BB, X86::IN8ri, 1).addImm(Port->getValue());
+ BuildMI(BB, X86::MOV8rr, 1, Result).addReg(X86::AL);
+ return Result;
+ case MVT::i16:
+ BuildMI(BB, X86::IN16ri, 1).addImm(Port->getValue());
+ BuildMI(BB, X86::MOV16rr, 1, Result).addReg(X86::AX);
+ return Result;
+ case MVT::i32:
+ BuildMI(BB, X86::IN32ri, 1).addImm(Port->getValue());
+ BuildMI(BB, X86::MOV32rr, 1, Result).addReg(X86::EAX);
+ return Result;
+ default: break;
+ }
+ }
+
+ // Now, move the I/O port address into the DX register and use the IN
+ // instruction to get the input data.
+ //
+ Tmp1 = SelectExpr(Node->getOperand(1));
+ BuildMI(BB, X86::MOV16rr, 1, X86::DX).addReg(Tmp1);
switch (Node->getValueType(0)) {
- default: assert(0 && "Unknown value type for call result!");
- case MVT::Other: return 1;
- case MVT::i1:
case MVT::i8:
+ BuildMI(BB, X86::IN8rr, 0);
BuildMI(BB, X86::MOV8rr, 1, Result).addReg(X86::AL);
- break;
+ return Result;
case MVT::i16:
+ BuildMI(BB, X86::IN16rr, 0);
BuildMI(BB, X86::MOV16rr, 1, Result).addReg(X86::AX);
- break;
+ return Result;
case MVT::i32:
+ BuildMI(BB, X86::IN32rr, 0);
BuildMI(BB, X86::MOV32rr, 1, Result).addReg(X86::EAX);
- if (Node->getValueType(1) == MVT::i32)
- BuildMI(BB, X86::MOV32rr, 1, Result+1).addReg(X86::EDX);
- break;
- case MVT::f64: // Floating-point return values live in %ST(0)
- ContainsFPCode = true;
- BuildMI(BB, X86::FpGETRESULT, 1, Result);
- break;
+ return Result;
+ default:
+ std::cerr << "Cannot do input on this data type";
+ exit(1);
}
- return Result+N.ResNo;
+
}
return 0;
X86::SHR8mi, X86::SHR16mi, X86::SHR32mi,
/*Have to put the reg in CL*/0, 0, 0,
};
-
+
const unsigned *TabPtr = 0;
switch (StVal.getOpcode()) {
default:
std::cerr << "CANNOT [mem] op= val: ";
StVal.Val->dump(); std::cerr << "\n";
+ case ISD::FMUL:
case ISD::MUL:
+ case ISD::FDIV:
case ISD::SDIV:
case ISD::UDIV:
+ case ISD::FREM:
case ISD::SREM:
case ISD::UREM: return false;
-
+
case ISD::ADD: TabPtr = ADDTAB; break;
case ISD::SUB: TabPtr = SUBTAB; break;
case ISD::AND: TabPtr = ANDTAB; break;
case ISD::SRA: TabPtr = SARTAB; break;
case ISD::SRL: TabPtr = SHRTAB; break;
}
-
+
// Handle: [mem] op= CST
SDOperand Op0 = StVal.getOperand(0);
SDOperand Op1 = StVal.getOperand(1);
- unsigned Opc;
+ unsigned Opc = 0;
if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Op1)) {
switch (Op0.getValueType()) { // Use Op0's type because of shifts.
default: break;
case MVT::i16: Opc = TabPtr[1]; break;
case MVT::i32: Opc = TabPtr[2]; break;
}
-
+
if (Opc) {
if (!ExprMap.insert(std::make_pair(TheLoad.getValue(1), 1)).second)
assert(0 && "Already emitted?");
} else {
SelectAddress(TheLoad.getOperand(1), AM);
Select(TheLoad.getOperand(0));
- }
+ }
if (StVal.getOpcode() == ISD::ADD) {
if (CN->getValue() == 1) {
}
}
}
-
+
addFullAddress(BuildMI(BB, Opc, 4+1),AM).addImm(CN->getValue());
return true;
}
}
-
+
// If we have [mem] = V op [mem], try to turn it into:
// [mem] = [mem] op V.
- if (Op1 == TheLoad && StVal.getOpcode() != ISD::SUB &&
+ if (Op1 == TheLoad &&
+ StVal.getOpcode() != ISD::SUB && StVal.getOpcode() != ISD::FSUB &&
StVal.getOpcode() != ISD::SHL && StVal.getOpcode() != ISD::SRA &&
StVal.getOpcode() != ISD::SRL)
std::swap(Op0, Op1);
-
+
if (Op0 != TheLoad) return false;
switch (Op0.getValueType()) {
return true;
}
+/// If node is a ret(tailcall) node, emit the specified tail call and return
+/// true, otherwise return false.
+///
+/// FIXME: This whole thing should be a post-legalize optimization pass which
+/// recognizes and transforms the dag. We don't want the selection phase doing
+/// this stuff!!
+///
+bool ISel::EmitPotentialTailCall(SDNode *RetNode) {
+ assert(RetNode->getOpcode() == ISD::RET && "Not a return");
+
+ SDOperand Chain = RetNode->getOperand(0);
+
+ // If this is a token factor node where one operand is a call, dig into it.
+ SDOperand TokFactor;
+ unsigned TokFactorOperand = 0;
+ if (Chain.getOpcode() == ISD::TokenFactor) {
+ for (unsigned i = 0, e = Chain.getNumOperands(); i != e; ++i)
+ if (Chain.getOperand(i).getOpcode() == ISD::CALLSEQ_END ||
+ Chain.getOperand(i).getOpcode() == X86ISD::TAILCALL) {
+ TokFactorOperand = i;
+ TokFactor = Chain;
+ Chain = Chain.getOperand(i);
+ break;
+ }
+ if (TokFactor.Val == 0) return false; // No call operand.
+ }
+
+ // Skip the CALLSEQ_END node if present.
+ if (Chain.getOpcode() == ISD::CALLSEQ_END)
+ Chain = Chain.getOperand(0);
+
+ // Is a tailcall the last control operation that occurs before the return?
+ if (Chain.getOpcode() != X86ISD::TAILCALL)
+ return false;
+
+ // If we return a value, is it the value produced by the call?
+ if (RetNode->getNumOperands() > 1) {
+ // Not returning the ret val of the call?
+ if (Chain.Val->getNumValues() == 1 ||
+ RetNode->getOperand(1) != Chain.getValue(1))
+ return false;
+
+ if (RetNode->getNumOperands() > 2) {
+ if (Chain.Val->getNumValues() == 2 ||
+ RetNode->getOperand(2) != Chain.getValue(2))
+ return false;
+ }
+ assert(RetNode->getNumOperands() <= 3);
+ }
+
+ // CalleeCallArgAmt - The total number of bytes used for the callee arg area.
+ // For FastCC, this will always be > 0.
+ unsigned CalleeCallArgAmt =
+ cast<ConstantSDNode>(Chain.getOperand(2))->getValue();
+
+ // CalleeCallArgPopAmt - The number of bytes in the call area popped by the
+ // callee. For FastCC this will always be > 0, for CCC this is always 0.
+ unsigned CalleeCallArgPopAmt =
+ cast<ConstantSDNode>(Chain.getOperand(3))->getValue();
+
+ // There are several cases we can handle here. First, if the caller and
+ // callee are both CCC functions, we can tailcall if the callee takes <= the
+ // number of argument bytes that the caller does.
+ if (CalleeCallArgPopAmt == 0 && // Callee is C CallingConv?
+ X86Lowering.getBytesToPopOnReturn() == 0) { // Caller is C CallingConv?
+ // Check to see if caller arg area size >= callee arg area size.
+ if (X86Lowering.getBytesCallerReserves() >= CalleeCallArgAmt) {
+ //std::cerr << "CCC TAILCALL UNIMP!\n";
+ // If TokFactor is non-null, emit all operands.
+
+ //EmitCCCToCCCTailCall(Chain.Val);
+ //return true;
+ }
+ return false;
+ }
+
+ // Second, if both are FastCC functions, we can always perform the tail call.
+ if (CalleeCallArgPopAmt && X86Lowering.getBytesToPopOnReturn()) {
+ // If TokFactor is non-null, emit all operands before the call.
+ if (TokFactor.Val) {
+ for (unsigned i = 0, e = TokFactor.getNumOperands(); i != e; ++i)
+ if (i != TokFactorOperand)
+ Select(TokFactor.getOperand(i));
+ }
+
+ EmitFastCCToFastCCTailCall(Chain.Val);
+ return true;
+ }
+
+ // We don't support mixed calls, due to issues with alignment. We could in
+ // theory handle some mixed calls from CCC -> FastCC if the stack is properly
+ // aligned (which depends on the number of arguments to the callee). TODO.
+ return false;
+}
+
+static SDOperand GetAdjustedArgumentStores(SDOperand Chain, int Offset,
+ SelectionDAG &DAG) {
+ MVT::ValueType StoreVT;
+ switch (Chain.getOpcode()) {
+ default: assert(0 && "Unexpected node!");
+ case ISD::CALLSEQ_START:
+ // If we found the start of the call sequence, we're done. We actually
+ // strip off the CALLSEQ_START node, to avoid generating the
+ // ADJCALLSTACKDOWN marker for the tail call.
+ return Chain.getOperand(0);
+ case ISD::TokenFactor: {
+ std::vector<SDOperand> Ops;
+ Ops.reserve(Chain.getNumOperands());
+ for (unsigned i = 0, e = Chain.getNumOperands(); i != e; ++i)
+ Ops.push_back(GetAdjustedArgumentStores(Chain.getOperand(i), Offset,DAG));
+ return DAG.getNode(ISD::TokenFactor, MVT::Other, Ops);
+ }
+ case ISD::STORE: // Normal store
+ StoreVT = Chain.getOperand(1).getValueType();
+ break;
+ case ISD::TRUNCSTORE: // FLOAT store
+ StoreVT = cast<VTSDNode>(Chain.getOperand(4))->getVT();
+ break;
+ }
+
+ SDOperand OrigDest = Chain.getOperand(2);
+ unsigned OrigOffset;
+
+ if (OrigDest.getOpcode() == ISD::CopyFromReg) {
+ OrigOffset = 0;
+ assert(cast<RegisterSDNode>(OrigDest.getOperand(1))->getReg() == X86::ESP);
+ } else {
+ // We expect only (ESP+C)
+ assert(OrigDest.getOpcode() == ISD::ADD &&
+ isa<ConstantSDNode>(OrigDest.getOperand(1)) &&
+ OrigDest.getOperand(0).getOpcode() == ISD::CopyFromReg &&
+ cast<RegisterSDNode>(OrigDest.getOperand(0).getOperand(1))->getReg()
+ == X86::ESP);
+ OrigOffset = cast<ConstantSDNode>(OrigDest.getOperand(1))->getValue();
+ }
+
+ // Compute the new offset from the incoming ESP value we wish to use.
+ unsigned NewOffset = OrigOffset + Offset;
+
+ unsigned OpSize = (MVT::getSizeInBits(StoreVT)+7)/8; // Bits -> Bytes
+ MachineFunction &MF = DAG.getMachineFunction();
+ int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, NewOffset);
+ SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
+
+ SDOperand InChain = GetAdjustedArgumentStores(Chain.getOperand(0), Offset,
+ DAG);
+ if (Chain.getOpcode() == ISD::STORE)
+ return DAG.getNode(ISD::STORE, MVT::Other, InChain, Chain.getOperand(1),
+ FIN);
+ assert(Chain.getOpcode() == ISD::TRUNCSTORE);
+ return DAG.getNode(ISD::TRUNCSTORE, MVT::Other, InChain, Chain.getOperand(1),
+ FIN, DAG.getSrcValue(NULL), DAG.getValueType(StoreVT));
+}
+
+
+/// EmitFastCCToFastCCTailCall - Given a tailcall in the tail position to a
+/// fastcc function from a fastcc function, emit the code to emit a 'proper'
+/// tail call.
+void ISel::EmitFastCCToFastCCTailCall(SDNode *TailCallNode) {
+ unsigned CalleeCallArgSize =
+ cast<ConstantSDNode>(TailCallNode->getOperand(2))->getValue();
+ unsigned CallerArgSize = X86Lowering.getBytesToPopOnReturn();
+
+ //std::cerr << "****\n*** EMITTING TAIL CALL!\n****\n";
+
+ // Adjust argument stores. Instead of storing to [ESP], f.e., store to frame
+ // indexes that are relative to the incoming ESP. If the incoming and
+ // outgoing arg sizes are the same we will store to [InESP] instead of
+ // [CurESP] and the ESP referenced will be relative to the incoming function
+ // ESP.
+ int ESPOffset = CallerArgSize-CalleeCallArgSize;
+ SDOperand AdjustedArgStores =
+ GetAdjustedArgumentStores(TailCallNode->getOperand(0), ESPOffset, *TheDAG);
+
+ // Copy the return address of the caller into a virtual register so we don't
+ // clobber it.
+ SDOperand RetVal;
+ if (ESPOffset) {
+ SDOperand RetValAddr = X86Lowering.getReturnAddressFrameIndex(*TheDAG);
+ RetVal = TheDAG->getLoad(MVT::i32, TheDAG->getEntryNode(),
+ RetValAddr, TheDAG->getSrcValue(NULL));
+ SelectExpr(RetVal);
+ }
+
+ // Codegen all of the argument stores.
+ Select(AdjustedArgStores);
+
+ if (RetVal.Val) {
+ // Emit a store of the saved ret value to the new location.
+ MachineFunction &MF = TheDAG->getMachineFunction();
+ int ReturnAddrFI = MF.getFrameInfo()->CreateFixedObject(4, ESPOffset-4);
+ SDOperand RetValAddr = TheDAG->getFrameIndex(ReturnAddrFI, MVT::i32);
+ Select(TheDAG->getNode(ISD::STORE, MVT::Other, TheDAG->getEntryNode(),
+ RetVal, RetValAddr));
+ }
+
+ // Get the destination value.
+ SDOperand Callee = TailCallNode->getOperand(1);
+ bool isDirect = isa<GlobalAddressSDNode>(Callee) ||
+ isa<ExternalSymbolSDNode>(Callee);
+ unsigned CalleeReg = 0;
+ if (!isDirect) CalleeReg = SelectExpr(Callee);
+
+ unsigned RegOp1 = 0;
+ unsigned RegOp2 = 0;
+
+ if (TailCallNode->getNumOperands() > 4) {
+ // The first value is passed in (a part of) EAX, the second in EDX.
+ RegOp1 = SelectExpr(TailCallNode->getOperand(4));
+ if (TailCallNode->getNumOperands() > 5)
+ RegOp2 = SelectExpr(TailCallNode->getOperand(5));
+
+ switch (TailCallNode->getOperand(4).getValueType()) {
+ default: assert(0 && "Bad thing to pass in regs");
+ case MVT::i1:
+ case MVT::i8:
+ BuildMI(BB, X86::MOV8rr, 1, X86::AL).addReg(RegOp1);
+ RegOp1 = X86::AL;
+ break;
+ case MVT::i16:
+ BuildMI(BB, X86::MOV16rr, 1,X86::AX).addReg(RegOp1);
+ RegOp1 = X86::AX;
+ break;
+ case MVT::i32:
+ BuildMI(BB, X86::MOV32rr, 1,X86::EAX).addReg(RegOp1);
+ RegOp1 = X86::EAX;
+ break;
+ }
+ if (RegOp2)
+ switch (TailCallNode->getOperand(5).getValueType()) {
+ default: assert(0 && "Bad thing to pass in regs");
+ case MVT::i1:
+ case MVT::i8:
+ BuildMI(BB, X86::MOV8rr, 1, X86::DL).addReg(RegOp2);
+ RegOp2 = X86::DL;
+ break;
+ case MVT::i16:
+ BuildMI(BB, X86::MOV16rr, 1, X86::DX).addReg(RegOp2);
+ RegOp2 = X86::DX;
+ break;
+ case MVT::i32:
+ BuildMI(BB, X86::MOV32rr, 1, X86::EDX).addReg(RegOp2);
+ RegOp2 = X86::EDX;
+ break;
+ }
+ }
+
+ // Adjust ESP.
+ if (ESPOffset)
+ BuildMI(BB, X86::ADJSTACKPTRri, 2,
+ X86::ESP).addReg(X86::ESP).addImm(ESPOffset);
+
+ // TODO: handle jmp [mem]
+ if (!isDirect) {
+ BuildMI(BB, X86::TAILJMPr, 1).addReg(CalleeReg);
+ } else if (GlobalAddressSDNode *GASD = dyn_cast<GlobalAddressSDNode>(Callee)){
+ BuildMI(BB, X86::TAILJMPd, 1).addGlobalAddress(GASD->getGlobal(), true);
+ } else {
+ ExternalSymbolSDNode *ESSDN = cast<ExternalSymbolSDNode>(Callee);
+ BuildMI(BB, X86::TAILJMPd, 1).addExternalSymbol(ESSDN->getSymbol(), true);
+ }
+ // ADD IMPLICIT USE RegOp1/RegOp2's
+}
+
void ISel::Select(SDOperand N) {
- unsigned Tmp1, Tmp2, Opc;
+ unsigned Tmp1 = 0, Tmp2 = 0, Opc = 0;
- // FIXME: Disable for our current expansion model!
- if (/*!N->hasOneUse() &&*/ !ExprMap.insert(std::make_pair(N, 1)).second)
+ if (!ExprMap.insert(std::make_pair(N, 1)).second)
return; // Already selected.
SDNode *Node = N.Val;
case ISD::EntryToken: return; // Noop
case ISD::TokenFactor:
if (Node->getNumOperands() == 2) {
- bool OneFirst =
+ bool OneFirst =
getRegPressure(Node->getOperand(1))>getRegPressure(Node->getOperand(0));
Select(Node->getOperand(OneFirst));
Select(Node->getOperand(!OneFirst));
}
return;
case ISD::CopyToReg:
- if (getRegPressure(N.getOperand(0)) > getRegPressure(N.getOperand(1))) {
+ if (getRegPressure(N.getOperand(0)) > getRegPressure(N.getOperand(2))) {
Select(N.getOperand(0));
- Tmp1 = SelectExpr(N.getOperand(1));
+ Tmp1 = SelectExpr(N.getOperand(2));
} else {
- Tmp1 = SelectExpr(N.getOperand(1));
+ Tmp1 = SelectExpr(N.getOperand(2));
Select(N.getOperand(0));
}
- Tmp2 = cast<RegSDNode>(N)->getReg();
-
+ Tmp2 = cast<RegisterSDNode>(N.getOperand(1))->getReg();
+
if (Tmp1 != Tmp2) {
- switch (N.getOperand(1).getValueType()) {
+ switch (N.getOperand(2).getValueType()) {
default: assert(0 && "Invalid type for operation!");
case MVT::i1:
case MVT::i8: Opc = X86::MOV8rr; break;
case MVT::i16: Opc = X86::MOV16rr; break;
case MVT::i32: Opc = X86::MOV32rr; break;
- case MVT::f64: Opc = X86::FpMOV; ContainsFPCode = true; break;
+ case MVT::f32: Opc = X86::MOVAPSrr; break;
+ case MVT::f64:
+ if (X86ScalarSSE) {
+ Opc = X86::MOVAPDrr;
+ } else {
+ Opc = X86::FpMOV;
+ ContainsFPCode = true;
+ }
+ break;
}
BuildMI(BB, Opc, 1, Tmp2).addReg(Tmp1);
}
return;
case ISD::RET:
+ if (N.getOperand(0).getOpcode() == ISD::CALLSEQ_END ||
+ N.getOperand(0).getOpcode() == X86ISD::TAILCALL ||
+ N.getOperand(0).getOpcode() == ISD::TokenFactor)
+ if (EmitPotentialTailCall(Node))
+ return;
+
switch (N.getNumOperands()) {
default:
assert(0 && "Unknown return instruction!");
case 3:
assert(N.getOperand(1).getValueType() == MVT::i32 &&
- N.getOperand(2).getValueType() == MVT::i32 &&
- "Unknown two-register value!");
+ N.getOperand(2).getValueType() == MVT::i32 &&
+ "Unknown two-register value!");
if (getRegPressure(N.getOperand(1)) > getRegPressure(N.getOperand(2))) {
Tmp1 = SelectExpr(N.getOperand(1));
Tmp2 = SelectExpr(N.getOperand(2));
BuildMI(BB, X86::MOV32rr, 1, X86::EAX).addReg(Tmp1);
BuildMI(BB, X86::MOV32rr, 1, X86::EDX).addReg(Tmp2);
- // Declare that EAX & EDX are live on exit.
- BuildMI(BB, X86::IMPLICIT_USE, 3).addReg(X86::EAX).addReg(X86::EDX)
- .addReg(X86::ESP);
break;
case 2:
if (getRegPressure(N.getOperand(0)) > getRegPressure(N.getOperand(1))) {
}
switch (N.getOperand(1).getValueType()) {
default: assert(0 && "All other types should have been promoted!!");
+ case MVT::f32:
+ if (X86ScalarSSE) {
+ // Spill the value to memory and reload it into top of stack.
+ unsigned Size = MVT::getSizeInBits(MVT::f32)/8;
+ MachineFunction *F = BB->getParent();
+ int FrameIdx = F->getFrameInfo()->CreateStackObject(Size, Size);
+ addFrameReference(BuildMI(BB, X86::MOVSSmr, 5), FrameIdx).addReg(Tmp1);
+ addFrameReference(BuildMI(BB, X86::FLD32m, 4, X86::FP0), FrameIdx);
+ BuildMI(BB, X86::FpSETRESULT, 1).addReg(X86::FP0);
+ ContainsFPCode = true;
+ } else {
+ assert(0 && "MVT::f32 only legal with scalar sse fp");
+ abort();
+ }
+ break;
case MVT::f64:
- BuildMI(BB, X86::FpSETRESULT, 1).addReg(Tmp1);
- // Declare that top-of-stack is live on exit
- BuildMI(BB, X86::IMPLICIT_USE, 2).addReg(X86::ST0).addReg(X86::ESP);
- break;
+ if (X86ScalarSSE) {
+ // Spill the value to memory and reload it into top of stack.
+ unsigned Size = MVT::getSizeInBits(MVT::f64)/8;
+ MachineFunction *F = BB->getParent();
+ int FrameIdx = F->getFrameInfo()->CreateStackObject(Size, Size);
+ addFrameReference(BuildMI(BB, X86::MOVSDmr, 5), FrameIdx).addReg(Tmp1);
+ addFrameReference(BuildMI(BB, X86::FLD64m, 4, X86::FP0), FrameIdx);
+ BuildMI(BB, X86::FpSETRESULT, 1).addReg(X86::FP0);
+ ContainsFPCode = true;
+ } else {
+ BuildMI(BB, X86::FpSETRESULT, 1).addReg(Tmp1);
+ }
+ break;
case MVT::i32:
- BuildMI(BB, X86::MOV32rr, 1, X86::EAX).addReg(Tmp1);
- BuildMI(BB, X86::IMPLICIT_USE, 2).addReg(X86::EAX).addReg(X86::ESP);
- break;
+ BuildMI(BB, X86::MOV32rr, 1, X86::EAX).addReg(Tmp1);
+ break;
}
break;
case 1:
Select(N.getOperand(0));
break;
}
- BuildMI(BB, X86::RET, 0); // Just emit a 'ret' instruction
+ if (X86Lowering.getBytesToPopOnReturn() == 0)
+ BuildMI(BB, X86::RET, 0); // Just emit a 'ret' instruction
+ else
+ BuildMI(BB, X86::RETI, 1).addImm(X86Lowering.getBytesToPopOnReturn());
return;
case ISD::BR: {
Select(N.getOperand(0));
ExprMap.erase(N);
SelectExpr(N);
return;
-
+ case ISD::READPORT:
case ISD::EXTLOAD:
case ISD::SEXTLOAD:
case ISD::ZEXTLOAD:
- case ISD::CALL:
case ISD::DYNAMIC_STACKALLOC:
+ case X86ISD::TAILCALL:
+ case X86ISD::CALL:
ExprMap.erase(N);
SelectExpr(N);
return;
+ case ISD::CopyFromReg:
+ case X86ISD::FILD64m:
+ ExprMap.erase(N);
+ SelectExpr(N.getValue(0));
+ return;
+
+ case X86ISD::FP_TO_INT16_IN_MEM:
+ case X86ISD::FP_TO_INT32_IN_MEM:
+ case X86ISD::FP_TO_INT64_IN_MEM: {
+ assert(N.getOperand(1).getValueType() == MVT::f64);
+ X86AddressMode AM;
+ Select(N.getOperand(0)); // Select the token chain
+
+ unsigned ValReg;
+ if (getRegPressure(N.getOperand(1)) > getRegPressure(N.getOperand(2))) {
+ ValReg = SelectExpr(N.getOperand(1));
+ SelectAddress(N.getOperand(2), AM);
+ } else {
+ SelectAddress(N.getOperand(2), AM);
+ ValReg = SelectExpr(N.getOperand(1));
+ }
+
+ // Change the floating point control register to use "round towards zero"
+ // mode when truncating to an integer value.
+ //
+ MachineFunction *F = BB->getParent();
+ int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2);
+ addFrameReference(BuildMI(BB, X86::FNSTCW16m, 4), CWFrameIdx);
+
+ // Load the old value of the high byte of the control word...
+ unsigned OldCW = MakeReg(MVT::i16);
+ addFrameReference(BuildMI(BB, X86::MOV16rm, 4, OldCW), CWFrameIdx);
+
+ // Set the high part to be round to zero...
+ addFrameReference(BuildMI(BB, X86::MOV16mi, 5), CWFrameIdx).addImm(0xC7F);
+
+ // Reload the modified control word now...
+ addFrameReference(BuildMI(BB, X86::FLDCW16m, 4), CWFrameIdx);
+
+ // Restore the memory image of control word to original value
+ addFrameReference(BuildMI(BB, X86::MOV16mr, 5), CWFrameIdx).addReg(OldCW);
+
+ // Get the X86 opcode to use.
+ switch (N.getOpcode()) {
+ case X86ISD::FP_TO_INT16_IN_MEM: Tmp1 = X86::FIST16m; break;
+ case X86ISD::FP_TO_INT32_IN_MEM: Tmp1 = X86::FIST32m; break;
+ case X86ISD::FP_TO_INT64_IN_MEM: Tmp1 = X86::FISTP64m; break;
+ }
+
+ addFullAddress(BuildMI(BB, Tmp1, 5), AM).addReg(ValReg);
+
+ // Reload the original control word now.
+ addFrameReference(BuildMI(BB, X86::FLDCW16m, 4), CWFrameIdx);
+ return;
+ }
- case ISD::TRUNCSTORE: { // truncstore chain, val, ptr :storety
- // On X86, we can represent all types except for Bool and Float natively.
+ case ISD::TRUNCSTORE: { // truncstore chain, val, ptr, SRCVALUE, storety
X86AddressMode AM;
- MVT::ValueType StoredTy = cast<MVTSDNode>(Node)->getExtraValueType();
+ MVT::ValueType StoredTy = cast<VTSDNode>(N.getOperand(4))->getVT();
assert((StoredTy == MVT::i1 || StoredTy == MVT::f32 ||
StoredTy == MVT::i16 /*FIXME: THIS IS JUST FOR TESTING!*/)
&& "Unsupported TRUNCSTORE for this target!");
switch (StoredTy) {
default: assert(0 && "Cannot truncstore this type!");
case MVT::i1: Opc = X86::MOV8mr; break;
- case MVT::f32: Opc = X86::FST32m; break;
+ case MVT::f32:
+ assert(!X86ScalarSSE && "Cannot truncstore scalar SSE regs");
+ Opc = X86::FST32m; break;
}
-
+
std::vector<std::pair<unsigned, unsigned> > RP;
RP.push_back(std::make_pair(getRegPressure(N.getOperand(0)), 0));
RP.push_back(std::make_pair(getRegPressure(N.getOperand(1)), 1));
RP.push_back(std::make_pair(getRegPressure(N.getOperand(2)), 2));
std::sort(RP.begin(), RP.end());
+ Tmp1 = 0; // Silence a warning.
for (unsigned i = 0; i != 3; ++i)
switch (RP[2-i].second) {
default: assert(0 && "Unknown operand number!");
case MVT::i8: Opc = X86::MOV8mi; break;
case MVT::i16: Opc = X86::MOV16mi; break;
case MVT::i32: Opc = X86::MOV32mi; break;
- case MVT::f64: break;
}
if (Opc) {
if (getRegPressure(N.getOperand(0)) > getRegPressure(N.getOperand(2))) {
addFullAddress(BuildMI(BB, Opc, 4+1), AM).addImm(CN->getValue());
return;
}
+ } else if (GlobalAddressSDNode *GA =
+ dyn_cast<GlobalAddressSDNode>(N.getOperand(1))) {
+ assert(GA->getValueType(0) == MVT::i32 && "Bad pointer operand");
+
+ if (getRegPressure(N.getOperand(0)) > getRegPressure(N.getOperand(2))) {
+ Select(N.getOperand(0));
+ SelectAddress(N.getOperand(2), AM);
+ } else {
+ SelectAddress(N.getOperand(2), AM);
+ Select(N.getOperand(0));
+ }
+ GlobalValue *GV = GA->getGlobal();
+ // For Darwin, external and weak symbols are indirect, so we want to load
+ // the value at address GV, not the value of GV itself.
+ if (Subtarget->getIndirectExternAndWeakGlobals() &&
+ (GV->hasWeakLinkage() || GV->isExternal())) {
+ Tmp1 = MakeReg(MVT::i32);
+ BuildMI(BB, X86::MOV32rm, 4, Tmp1).addReg(0).addZImm(1).addReg(0)
+ .addGlobalAddress(GV, false, 0);
+ addFullAddress(BuildMI(BB, X86::MOV32mr, 4+1),AM).addReg(Tmp1);
+ } else {
+ addFullAddress(BuildMI(BB, X86::MOV32mi, 4+1),AM).addGlobalAddress(GV);
+ }
+ return;
}
// Check to see if this is a load/op/store combination.
case MVT::i8: Opc = X86::MOV8mr; break;
case MVT::i16: Opc = X86::MOV16mr; break;
case MVT::i32: Opc = X86::MOV32mr; break;
- case MVT::f64: Opc = X86::FST64m; break;
+ case MVT::f32: Opc = X86::MOVSSmr; break;
+ case MVT::f64: Opc = X86ScalarSSE ? X86::MOVSDmr : X86::FST64m; break;
}
-
+
std::vector<std::pair<unsigned, unsigned> > RP;
RP.push_back(std::make_pair(getRegPressure(N.getOperand(0)), 0));
RP.push_back(std::make_pair(getRegPressure(N.getOperand(1)), 1));
RP.push_back(std::make_pair(getRegPressure(N.getOperand(2)), 2));
std::sort(RP.begin(), RP.end());
+ Tmp1 = 0; // Silence a warning.
for (unsigned i = 0; i != 3; ++i)
switch (RP[2-i].second) {
default: assert(0 && "Unknown operand number!");
addFullAddress(BuildMI(BB, Opc, 4+1), AM).addReg(Tmp1);
return;
}
- case ISD::ADJCALLSTACKDOWN:
- case ISD::ADJCALLSTACKUP:
+ case ISD::CALLSEQ_START:
Select(N.getOperand(0));
+ // Stack amount
Tmp1 = cast<ConstantSDNode>(N.getOperand(1))->getValue();
-
- Opc = N.getOpcode() == ISD::ADJCALLSTACKDOWN ? X86::ADJCALLSTACKDOWN :
- X86::ADJCALLSTACKUP;
- BuildMI(BB, Opc, 1).addImm(Tmp1);
+ BuildMI(BB, X86::ADJCALLSTACKDOWN, 1).addImm(Tmp1);
+ return;
+ case ISD::CALLSEQ_END:
+ Select(N.getOperand(0));
return;
case ISD::MEMSET: {
Select(N.getOperand(0)); // Select the chain.
BuildMI(BB, Opcode, 0);
return;
}
- case ISD::MEMCPY:
+ case ISD::MEMCPY: {
Select(N.getOperand(0)); // Select the chain.
unsigned Align =
(unsigned)cast<ConstantSDNode>(Node->getOperand(4))->getValue();
BuildMI(BB, Opcode, 0);
return;
}
+ case ISD::WRITEPORT:
+ if (Node->getOperand(2).getValueType() != MVT::i16) {
+ std::cerr << "llvm.writeport: Address size is not 16 bits\n";
+ exit(1);
+ }
+ Select(Node->getOperand(0)); // Emit the chain.
+
+ Tmp1 = SelectExpr(Node->getOperand(1));
+ switch (Node->getOperand(1).getValueType()) {
+ case MVT::i8:
+ BuildMI(BB, X86::MOV8rr, 1, X86::AL).addReg(Tmp1);
+ Tmp2 = X86::OUT8ir; Opc = X86::OUT8rr;
+ break;
+ case MVT::i16:
+ BuildMI(BB, X86::MOV16rr, 1, X86::AX).addReg(Tmp1);
+ Tmp2 = X86::OUT16ir; Opc = X86::OUT16rr;
+ break;
+ case MVT::i32:
+ BuildMI(BB, X86::MOV32rr, 1, X86::EAX).addReg(Tmp1);
+ Tmp2 = X86::OUT32ir; Opc = X86::OUT32rr;
+ break;
+ default:
+ std::cerr << "llvm.writeport: invalid data type for X86 target";
+ exit(1);
+ }
+
+ // If the port is a single-byte constant, use the immediate form.
+ if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Node->getOperand(2)))
+ if ((CN->getValue() & 255) == CN->getValue()) {
+ BuildMI(BB, Tmp2, 1).addImm(CN->getValue());
+ return;
+ }
+
+ // Otherwise, move the I/O port address into the DX register.
+ unsigned Reg = SelectExpr(Node->getOperand(2));
+ BuildMI(BB, X86::MOV16rr, 1, X86::DX).addReg(Reg);
+ BuildMI(BB, Opc, 0);
+ return;
+ }
assert(0 && "Should not be reached!");
}
/// description file.
///
FunctionPass *llvm::createX86PatternInstructionSelector(TargetMachine &TM) {
- return new ISel(TM);
+ return new ISel(TM);
}
projects / oota-llvm.git / blobdiff