setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
setOperationAction(ISD::SEXTLOAD , MVT::i1 , Expand);
- setOperationAction(ISD::SREM , MVT::f64 , Expand);
+ setOperationAction(ISD::FREM , MVT::f64 , Expand);
setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
setOperationAction(ISD::CTTZ , MVT::i8 , Expand);
setOperationAction(ISD::CTLZ , MVT::i8 , Expand);
setOperationAction(ISD::FCOS , MVT::f64, Expand);
setOperationAction(ISD::FABS , MVT::f64, Expand);
setOperationAction(ISD::FNEG , MVT::f64, Expand);
- setOperationAction(ISD::SREM , MVT::f64, Expand);
+ setOperationAction(ISD::FREM , MVT::f64, Expand);
setOperationAction(ISD::FSIN , MVT::f32, Expand);
setOperationAction(ISD::FCOS , MVT::f32, Expand);
setOperationAction(ISD::FABS , MVT::f32, Expand);
setOperationAction(ISD::FNEG , MVT::f32, Expand);
- setOperationAction(ISD::SREM , MVT::f32, Expand);
+ setOperationAction(ISD::FREM , MVT::f32, Expand);
addLegalFPImmediate(+0.0); // xorps / xorpd
} else {
maxStoresPerMemSet = 8; // For %llvm.memset -> sequence of stores
maxStoresPerMemCpy = 8; // For %llvm.memcpy -> sequence of stores
maxStoresPerMemMove = 8; // For %llvm.memmove -> sequence of stores
- allowUnalignedStores = true; // x86 supports it!
+ allowUnalignedMemoryAccesses = true; // x86 supports it!
}
// Return the number of bytes that a function should pop when it returns (in
}
void ISel::EmitFunctionEntryCode(Function &Fn, MachineFunction &MF) {
- // If this function has live-in values, emit the copies from pregs to vregs at
- // the top of the function, before anything else.
- MachineBasicBlock *BB = MF.begin();
- if (MF.livein_begin() != MF.livein_end()) {
- SSARegMap *RegMap = MF.getSSARegMap();
- for (MachineFunction::livein_iterator LI = MF.livein_begin(),
- E = MF.livein_end(); LI != E; ++LI) {
- const TargetRegisterClass *RC = RegMap->getRegClass(LI->second);
- if (RC == X86::R8RegisterClass) {
- BuildMI(BB, X86::MOV8rr, 1, LI->second).addReg(LI->first);
- } else if (RC == X86::R16RegisterClass) {
- BuildMI(BB, X86::MOV16rr, 1, LI->second).addReg(LI->first);
- } else if (RC == X86::R32RegisterClass) {
- BuildMI(BB, X86::MOV32rr, 1, LI->second).addReg(LI->first);
- } else if (RC == X86::RFPRegisterClass) {
- BuildMI(BB, X86::FpMOV, 1, LI->second).addReg(LI->first);
- } else if (RC == X86::RXMMRegisterClass) {
- BuildMI(BB, X86::MOVAPDrr, 1, LI->second).addReg(LI->first);
- } else {
- assert(0 && "Unknown regclass!");
- }
- }
- }
-
-
// If this is main, emit special code for main.
+ MachineBasicBlock *BB = MF.begin();
if (Fn.hasExternalLinkage() && Fn.getName() == "main")
EmitSpecialCodeForMain(BB, MF.getFrameInfo());
}
unsigned ISel::SelectExpr(SDOperand N) {
unsigned Result;
- unsigned Tmp1, Tmp2, Tmp3;
- unsigned Opc = 0;
+ unsigned Tmp1 = 0, Tmp2 = 0, Tmp3 = 0, Opc = 0;
SDNode *Node = N.Val;
SDOperand Op0, Op1;
addFrameReference(BuildMI(BB, X86::LEA32r, 4, Result), (int)Tmp1);
return Result;
case ISD::ConstantPool:
- Tmp1 = cast<ConstantPoolSDNode>(N)->getIndex();
+ Tmp1 = BB->getParent()->getConstantPool()->
+ getConstantPoolIndex(cast<ConstantPoolSDNode>(N)->get());
addConstantPoolReference(BuildMI(BB, X86::LEA32r, 4, Result), Tmp1);
return Result;
case ISD::ConstantFP:
BuildMI(BB, X86::MOV32ri, 1, Result).addExternalSymbol(Sym);
return Result;
}
+ case ISD::ANY_EXTEND: // treat any extend like zext
case ISD::ZERO_EXTEND: {
int DestIs16 = N.getValueType() == MVT::i16;
int SrcIs16 = N.getOperand(0).getValueType() == MVT::i16;
}
return Result;
+ case ISD::FADD:
case ISD::ADD:
Op0 = N.getOperand(0);
Op1 = N.getOperand(1);
return Result;
}
+ case ISD::FSUB:
+ case ISD::FMUL:
case ISD::SUB:
case ISD::MUL:
case ISD::AND:
}
switch (Node->getOpcode()) {
default: assert(0 && "Unreachable!");
+ case ISD::FSUB:
case ISD::SUB: Opc = X86ScalarSSE ? SSE_SUBTab[Opc] : SUBTab[Opc]; break;
+ case ISD::FMUL:
case ISD::MUL: Opc = X86ScalarSSE ? SSE_MULTab[Opc] : MULTab[Opc]; break;
case ISD::AND: Opc = ANDTab[Opc]; break;
case ISD::OR: Opc = ORTab[Opc]; break;
}
if (isFoldableLoad(Op0, Op1, true))
- if (Node->getOpcode() != ISD::SUB) {
+ if (Node->getOpcode() != ISD::SUB && Node->getOpcode() != ISD::FSUB) {
std::swap(Op0, Op1);
goto FoldOps;
} else {
}
switch (Node->getOpcode()) {
default: assert(0 && "Unreachable!");
+ case ISD::FSUB:
case ISD::SUB: Opc = X86ScalarSSE ? SSE_SUBTab[Opc] : SUBTab[Opc]; break;
+ case ISD::FMUL:
case ISD::MUL: Opc = X86ScalarSSE ? SSE_MULTab[Opc] : MULTab[Opc]; break;
case ISD::AND: Opc = ANDTab[Opc]; break;
case ISD::OR: Opc = ORTab[Opc]; break;
}
switch (Node->getOpcode()) {
default: assert(0 && "Unreachable!");
+ case ISD::FSUB:
case ISD::SUB: Opc = X86ScalarSSE ? SSE_SUBTab[Opc] : SUBTab[Opc]; break;
+ case ISD::FMUL:
case ISD::MUL: Opc = X86ScalarSSE ? SSE_MULTab[Opc] : MULTab[Opc]; break;
case ISD::AND: Opc = ANDTab[Opc]; break;
case ISD::OR: Opc = ORTab[Opc]; break;
N.getValueType(), Result);
return Result;
+ case ISD::FDIV:
+ case ISD::FREM:
case ISD::SDIV:
case ISD::UDIV:
case ISD::SREM:
assert((N.getOpcode() != ISD::SREM || MVT::isInteger(N.getValueType())) &&
"We don't support this operator!");
- if (N.getOpcode() == ISD::SDIV) {
+ if (N.getOpcode() == ISD::SDIV || N.getOpcode() == ISD::FDIV) {
// We can fold loads into FpDIVs, but not really into any others.
if (N.getValueType() == MVT::f64 && !X86ScalarSSE) {
// Check for reversed and unreversed DIV.
case MVT::i32: Opc = X86::SAR32rCL; break;
}
BuildMI(BB, X86::MOV8rr, 1, X86::CL).addReg(Tmp2);
- BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
+ BuildMI(BB, Opc, 1, Result).addReg(Tmp1);
return Result;
case ISD::SETCC:
}
if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N.getOperand(1))){
+ unsigned CPIdx = BB->getParent()->getConstantPool()->
+ getConstantPoolIndex(CP->get());
Select(N.getOperand(0));
- addConstantPoolReference(BuildMI(BB, Opc, 4, Result), CP->getIndex());
+ addConstantPoolReference(BuildMI(BB, Opc, 4, Result), CPIdx);
} else {
X86AddressMode AM;
if (Node->getValueType(0) == MVT::f64) {
assert(cast<VTSDNode>(Node->getOperand(3))->getVT() == MVT::f32 &&
"Bad EXTLOAD!");
- addConstantPoolReference(BuildMI(BB, X86::FLD32m, 4, Result),
- CP->getIndex());
+ unsigned CPIdx = BB->getParent()->getConstantPool()->
+ getConstantPoolIndex(CP->get());
+
+ addConstantPoolReference(BuildMI(BB, X86::FLD32m, 4, Result), CPIdx);
return Result;
}
default:
std::cerr << "CANNOT [mem] op= val: ";
StVal.Val->dump(); std::cerr << "\n";
+ case ISD::FMUL:
case ISD::MUL:
+ case ISD::FDIV:
case ISD::SDIV:
case ISD::UDIV:
+ case ISD::FREM:
case ISD::SREM:
case ISD::UREM: return false;
// If we have [mem] = V op [mem], try to turn it into:
// [mem] = [mem] op V.
- if (Op1 == TheLoad && StVal.getOpcode() != ISD::SUB &&
+ if (Op1 == TheLoad &&
+ StVal.getOpcode() != ISD::SUB && StVal.getOpcode() != ISD::FSUB &&
StVal.getOpcode() != ISD::SHL && StVal.getOpcode() != ISD::SRA &&
StVal.getOpcode() != ISD::SRL)
std::swap(Op0, Op1);
SelectionDAG &DAG) {
MVT::ValueType StoreVT;
switch (Chain.getOpcode()) {
+ default: assert(0 && "Unexpected node!");
case ISD::CALLSEQ_START:
// If we found the start of the call sequence, we're done. We actually
// strip off the CALLSEQ_START node, to avoid generating the
void ISel::Select(SDOperand N) {
- unsigned Tmp1, Tmp2, Opc;
+ unsigned Tmp1 = 0, Tmp2 = 0, Opc = 0;
if (!ExprMap.insert(std::make_pair(N, 1)).second)
return; // Already selected.
projects / oota-llvm.git / blobdiff