using namespace MOTy; // Get Use, Def, UseAndDef
+
+/// BMI - A special BuildMI variant that takes an iterator to insert the
+/// instruction at as well as a basic block.
+/// this is the version for when you have a destination register in mind.
+inline static MachineInstrBuilder BMI(MachineBasicBlock *MBB,
+ MachineBasicBlock::iterator &I,
+ MachineOpCode Opcode,
+ unsigned NumOperands,
+ unsigned DestReg) {
+ assert(I >= MBB->begin() && I <= MBB->end() && "Bad iterator!");
+ MachineInstr *MI = new MachineInstr(Opcode, NumOperands+1, true, true);
+ I = ++MBB->insert(I, MI);
+ return MachineInstrBuilder(MI).addReg(DestReg, MOTy::Def);
+}
+
+/// BMI - A special BuildMI variant that takes an iterator to insert the
+/// instruction at as well as a basic block.
+inline static MachineInstrBuilder BMI(MachineBasicBlock *MBB,
+ MachineBasicBlock::iterator &I,
+ MachineOpCode Opcode,
+ unsigned NumOperands) {
+ assert(I > MBB->begin() && I <= MBB->end() && "Bad iterator!");
+ MachineInstr *MI = new MachineInstr(Opcode, NumOperands, true, true);
+ I = ++MBB->insert(I, MI);
+ return MachineInstrBuilder(MI);
+}
+
+
namespace {
struct ISel : public FunctionPass, InstVisitor<ISel> {
TargetMachine &TM;
unsigned CurReg;
std::map<Value*, unsigned> RegMap; // Mapping between Val's and SSA Regs
+ // MBBMap - Mapping between LLVM BB -> Machine BB
+ std::map<const BasicBlock*, MachineBasicBlock*> MBBMap;
+
ISel(TargetMachine &tm)
: TM(tm), F(0), BB(0), CurReg(MRegisterInfo::FirstVirtualRegister) {}
///
bool runOnFunction(Function &Fn) {
F = &MachineFunction::construct(&Fn, TM);
+
+ for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
+ F->getBasicBlockList().push_back(MBBMap[I] = new MachineBasicBlock(I));
+
+ // Instruction select everything except PHI nodes
visit(Fn);
+
+ // Select the PHI nodes
+ SelectPHINodes();
+
RegMap.clear();
+ MBBMap.clear();
CurReg = MRegisterInfo::FirstVirtualRegister;
F = 0;
return false; // We never modify the LLVM itself.
}
+ virtual const char *getPassName() const {
+ return "X86 Simple Instruction Selection";
+ }
+
/// visitBasicBlock - This method is called when we are visiting a new basic
/// block. This simply creates a new MachineBasicBlock to emit code into
/// and adds it to the current MachineFunction. Subsequent visit* for
/// instructions will be invoked for all instructions in the basic block.
///
void visitBasicBlock(BasicBlock &LLVM_BB) {
- BB = new MachineBasicBlock(&LLVM_BB);
- // FIXME: Use the auto-insert form when it's available
- F->getBasicBlockList().push_back(BB);
+ BB = MBBMap[&LLVM_BB];
}
+
+ /// SelectPHINodes - Insert machine code to generate phis. This is tricky
+ /// because we have to generate our sources into the source basic blocks,
+ /// not the current one.
+ ///
+ void SelectPHINodes();
+
// Visitation methods for various instructions. These methods simply emit
// fixed X86 code for each instruction.
//
void visitSimpleBinary(BinaryOperator &B, unsigned OpcodeClass);
void visitAdd(BinaryOperator &B) { visitSimpleBinary(B, 0); }
void visitSub(BinaryOperator &B) { visitSimpleBinary(B, 1); }
- void doMultiply(unsigned destReg, const Type *resultType,
+ void doMultiply(MachineBasicBlock *MBB, MachineBasicBlock::iterator &MBBI,
+ unsigned destReg, const Type *resultType,
unsigned op0Reg, unsigned op1Reg);
void visitMul(BinaryOperator &B);
// Other operators
void visitShiftInst(ShiftInst &I);
- void visitPHINode(PHINode &I);
+ void visitPHINode(PHINode &I) {} // PHI nodes handled by second pass
void visitCastInst(CastInst &I);
void visitInstruction(Instruction &I) {
// emitGEPOperation - Common code shared between visitGetElementPtrInst and
// constant expression GEP support.
//
- void emitGEPOperation(Value *Src, User::op_iterator IdxBegin,
+ void emitGEPOperation(MachineBasicBlock *BB, MachineBasicBlock::iterator&IP,
+ Value *Src, User::op_iterator IdxBegin,
User::op_iterator IdxEnd, unsigned TargetReg);
/// copyConstantToRegister - Output the instructions required to put the
/// specified constant into the specified register.
///
- void copyConstantToRegister(Constant *C, unsigned Reg);
+ void copyConstantToRegister(MachineBasicBlock *MBB,
+ MachineBasicBlock::iterator &MBBI,
+ Constant *C, unsigned Reg);
/// makeAnotherReg - This method returns the next register number
/// we haven't yet used.
///
unsigned getReg(Value &V) { return getReg(&V); } // Allow references
unsigned getReg(Value *V) {
+ // Just append to the end of the current bb.
+ MachineBasicBlock::iterator It = BB->end();
+ return getReg(V, BB, It);
+ }
+ unsigned getReg(Value *V, MachineBasicBlock *MBB,
+ MachineBasicBlock::iterator &IPt) {
unsigned &Reg = RegMap[V];
if (Reg == 0) {
Reg = makeAnotherReg(V->getType());
// the register here...
//
if (Constant *C = dyn_cast<Constant>(V)) {
- copyConstantToRegister(C, Reg);
+ copyConstantToRegister(MBB, IPt, C, Reg);
} else if (GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
// Move the address of the global into the register
- BuildMI(BB, X86::MOVir32, 1, Reg).addReg(GV);
+ BMI(MBB, IPt, X86::MOVir32, 1, Reg).addReg(GV);
} else if (Argument *A = dyn_cast<Argument>(V)) {
// Find the position of the argument in the argument list.
const Function *f = F->getFunction ();
// [EBP + 4] -- return address
// [EBP + 8] -- first argument (leftmost lexically)
// So we want to start with counter = 2.
- int counter = 2, argPosition = -1;
+ int counter = 2, argPos = -1;
for (Function::const_aiterator ai = f->abegin (), ae = f->aend ();
ai != ae; ++ai) {
if (&(*ai) == A) {
- argPosition = counter;
+ argPos = counter;
break; // Only need to find it once. ;-)
}
++counter;
}
- assert (argPosition != -1
+ assert (argPos != -1
&& "Argument not found in current function's argument list");
- // Load it out of the stack frame at EBP + 4*argPosition.
- addRegOffset (BuildMI (BB, X86::MOVmr32, 4, Reg), X86::EBP, 4*argPosition);
+ // Load it out of the stack frame at EBP + 4*argPos.
+ addRegOffset(BMI(MBB, IPt, X86::MOVmr32, 4, Reg), X86::EBP, 4*argPos);
}
return Reg;
}
}
+// getClassB - Just like getClass, but treat boolean values as bytes.
+static inline TypeClass getClassB(const Type *Ty) {
+ if (Ty == Type::BoolTy) return cByte;
+ return getClass(Ty);
+}
+
/// copyConstantToRegister - Output the instructions required to put the
/// specified constant into the specified register.
///
-void ISel::copyConstantToRegister(Constant *C, unsigned R) {
+void ISel::copyConstantToRegister(MachineBasicBlock *MBB,
+ MachineBasicBlock::iterator &IP,
+ Constant *C, unsigned R) {
if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
if (CE->getOpcode() == Instruction::GetElementPtr) {
- emitGEPOperation(CE->getOperand(0), CE->op_begin()+1, CE->op_end(), R);
+ emitGEPOperation(MBB, IP, CE->getOperand(0),
+ CE->op_begin()+1, CE->op_end(), R);
return;
}
}
if (C->getType()->isIntegral()) {
- unsigned Class = getClass(C->getType());
+ unsigned Class = getClassB(C->getType());
assert(Class != 3 && "Type not handled yet!");
static const unsigned IntegralOpcodeTab[] = {
X86::MOVir8, X86::MOVir16, X86::MOVir32
};
- if (C->getType()->isSigned()) {
+ if (C->getType() == Type::BoolTy) {
+ BMI(MBB, IP, X86::MOVir8, 1, R).addZImm(C == ConstantBool::True);
+ } else if (C->getType()->isSigned()) {
ConstantSInt *CSI = cast<ConstantSInt>(C);
- BuildMI(BB, IntegralOpcodeTab[Class], 1, R).addSImm(CSI->getValue());
+ BMI(MBB, IP, IntegralOpcodeTab[Class], 1, R).addSImm(CSI->getValue());
} else {
ConstantUInt *CUI = cast<ConstantUInt>(C);
- BuildMI(BB, IntegralOpcodeTab[Class], 1, R).addZImm(CUI->getValue());
+ BMI(MBB, IP, IntegralOpcodeTab[Class], 1, R).addZImm(CUI->getValue());
}
- } else if (isa <ConstantPointerNull> (C)) {
+ } else if (isa<ConstantPointerNull>(C)) {
// Copy zero (null pointer) to the register.
- BuildMI (BB, X86::MOVir32, 1, R).addZImm(0);
+ BMI(MBB, IP, X86::MOVir32, 1, R).addZImm(0);
} else if (ConstantPointerRef *CPR = dyn_cast<ConstantPointerRef>(C)) {
- unsigned SrcReg = getReg(CPR->getValue());
- BuildMI (BB, X86::MOVrr32, 1, R).addReg(SrcReg);
+ unsigned SrcReg = getReg(CPR->getValue(), MBB, IP);
+ BMI(MBB, IP, X86::MOVrr32, 1, R).addReg(SrcReg);
} else {
std::cerr << "Offending constant: " << C << "\n";
assert(0 && "Type not handled yet!");
}
}
+/// SelectPHINodes - Insert machine code to generate phis. This is tricky
+/// because we have to generate our sources into the source basic blocks, not
+/// the current one.
+///
+void ISel::SelectPHINodes() {
+ const Function &LF = *F->getFunction(); // The LLVM function...
+ for (Function::const_iterator I = LF.begin(), E = LF.end(); I != E; ++I) {
+ const BasicBlock *BB = I;
+ MachineBasicBlock *MBB = MBBMap[I];
+
+ // Loop over all of the PHI nodes in the LLVM basic block...
+ unsigned NumPHIs = 0;
+ for (BasicBlock::const_iterator I = BB->begin();
+ PHINode *PN = (PHINode*)dyn_cast<PHINode>(&*I); ++I) {
+ // Create a new machine instr PHI node, and insert it.
+ MachineInstr *MI = BuildMI(X86::PHI, PN->getNumOperands(), getReg(*PN));
+ MBB->insert(MBB->begin()+NumPHIs++, MI); // Insert it at the top of the BB
+
+ for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
+ MachineBasicBlock *PredMBB = MBBMap[PN->getIncomingBlock(i)];
+
+ // Get the incoming value into a virtual register. If it is not already
+ // available in a virtual register, insert the computation code into
+ // PredMBB
+ //
+
+ MachineBasicBlock::iterator PI = PredMBB->begin();
+ while ((*PI)->getOpcode() == X86::PHI) ++PI;
+
+ MI->addRegOperand(getReg(PN->getIncomingValue(i), PredMBB, PI));
+ MI->addMachineBasicBlockOperand(PredMBB);
+ }
+ }
+ }
+}
+
+
/// SetCC instructions - Here we just emit boilerplate code to set a byte-sized
/// register, then move it to wherever the result should be.
break;
}
}
- // Emit a CALL instruction with PC-relative displacement.
- BuildMI (BB, X86::CALLpcrel32, 1).addPCDisp (CI.getCalledValue ());
+
+ if (Function *F = CI.getCalledFunction()) {
+ // Emit a CALL instruction with PC-relative displacement.
+ BuildMI(BB, X86::CALLpcrel32, 1).addPCDisp(F);
+ } else {
+ unsigned Reg = getReg(CI.getCalledValue());
+ BuildMI(BB, X86::CALLr32, 1).addReg(Reg);
+ }
// Adjust the stack by `bytesPushed' amount if non-zero
if (bytesPushed > 0)
/// doMultiply - Emit appropriate instructions to multiply together
/// the registers op0Reg and op1Reg, and put the result in destReg.
/// The type of the result should be given as resultType.
-void
-ISel::doMultiply(unsigned destReg, const Type *resultType,
- unsigned op0Reg, unsigned op1Reg)
-{
+void ISel::doMultiply(MachineBasicBlock *MBB, MachineBasicBlock::iterator &MBBI,
+ unsigned destReg, const Type *resultType,
+ unsigned op0Reg, unsigned op1Reg) {
unsigned Class = getClass (resultType);
// FIXME:
// Emit a MOV to put the first operand into the appropriately-sized
// subreg of EAX.
- BuildMI (BB, MovOpcode[Class], 1, Reg).addReg (op0Reg);
+ BMI(MBB, MBBI, MovOpcode[Class], 1, Reg).addReg (op0Reg);
// Emit the appropriate multiply instruction.
- BuildMI (BB, MulOpcode[Class], 1).addReg (op1Reg);
+ BMI(MBB, MBBI, MulOpcode[Class], 1).addReg (op1Reg);
// Emit another MOV to put the result into the destination register.
- BuildMI (BB, MovOpcode[Class], 1, destReg).addReg (Reg);
+ BMI(MBB, MBBI, MovOpcode[Class], 1, destReg).addReg (Reg);
}
/// visitMul - Multiplies are not simple binary operators because they must deal
/// with the EAX register explicitly.
///
void ISel::visitMul(BinaryOperator &I) {
- doMultiply (getReg (I), I.getType (),
- getReg (I.getOperand (0)), getReg (I.getOperand (1)));
+ unsigned DestReg = getReg(I);
+ unsigned Op0Reg = getReg(I.getOperand(0));
+ unsigned Op1Reg = getReg(I.getOperand(1));
+ MachineBasicBlock::iterator MBBI = BB->end();
+ doMultiply(BB, MBBI, DestReg, I.getType(), Op0Reg, Op1Reg);
}
}
-/// visitPHINode - Turn an LLVM PHI node into an X86 PHI node...
-///
-void ISel::visitPHINode(PHINode &PN) {
- MachineInstr *MI = BuildMI(BB, X86::PHI, PN.getNumOperands(), getReg(PN));
-
- for (unsigned i = 0, e = PN.getNumIncomingValues(); i != e; ++i) {
- // FIXME: This will put constants after the PHI nodes in the block, which
- // is invalid. They should be put inline into the PHI node eventually.
- //
- MI->addRegOperand(getReg(PN.getIncomingValue(i)));
- MI->addPCDispOperand(PN.getIncomingBlock(i));
- }
-}
-
/// visitCastInst - Here we have various kinds of copying with or without
/// sign extension going on.
void
// 4) cast {int, uint, ptr} to {short, ushort}
// cast {int, uint, ptr} to {sbyte, ubyte}
// cast {short, ushort} to {sbyte, ubyte}
- //
+
// 1) Implement casts to bool by using compare on the operand followed
// by set if not zero on the result.
if (targetType == Type::BoolTy)
BuildMI (BB, X86::SETNEr, 1, destReg);
return;
}
+
// 2) Implement casts between values of the same type class (as determined
// by getClass) by using a register-to-register move.
- unsigned int srcClass = getClass (sourceType);
- unsigned int targClass = getClass (targetType);
+ unsigned srcClass = getClassB (sourceType);
+ unsigned targClass = getClass (targetType);
static const unsigned regRegMove[] = {
X86::MOVrr8, X86::MOVrr16, X86::MOVrr32
};
- if ((srcClass < 3) && (targClass < 3) && (srcClass == targClass))
+ if ((srcClass < cLong) && (targClass < cLong) && (srcClass == targClass))
{
BuildMI (BB, regRegMove[srcClass], 1, destReg).addReg (operandReg);
return;
// 3) Handle cast of SMALLER int to LARGER int using a move with sign
// extension or zero extension, depending on whether the source type
// was signed.
- if ((srcClass < 3) && (targClass < 3) && (srcClass < targClass))
+ if ((srcClass < cLong) && (targClass < cLong) && (srcClass < targClass))
{
static const unsigned ops[] = {
X86::MOVSXr16r8, X86::MOVSXr32r8, X86::MOVSXr32r16,
}
// 4) Handle cast of LARGER int to SMALLER int using a move to EAX
// followed by a move out of AX or AL.
- if ((srcClass < 3) && (targClass < 3) && (srcClass > targClass))
+ if ((srcClass < cLong) && (targClass < cLong) && (srcClass > targClass))
{
static const unsigned AReg[] = { X86::AL, X86::AX, X86::EAX };
BuildMI (BB, regRegMove[srcClass], 1,
visitInstruction (CI);
}
+// ExactLog2 - This function solves for (Val == 1 << (N-1)) and returns N. It
+// returns zero when the input is not exactly a power of two.
+static unsigned ExactLog2(unsigned Val) {
+ if (Val == 0) return 0;
+ unsigned Count = 0;
+ while (Val != 1) {
+ if (Val & 1) return 0;
+ Val >>= 1;
+ ++Count;
+ }
+ return Count+1;
+}
+
/// visitGetElementPtrInst - I don't know, most programs don't have
/// getelementptr instructions, right? That means we can put off
/// implementing this, right? Right. This method emits machine
void
ISel::visitGetElementPtrInst (GetElementPtrInst &I)
{
- emitGEPOperation(I.getOperand(0), I.op_begin()+1, I.op_end(), getReg(I));
+ unsigned outputReg = getReg (I);
+ MachineBasicBlock::iterator MI = BB->end();
+ emitGEPOperation(BB, MI, I.getOperand(0),
+ I.op_begin()+1, I.op_end(), outputReg);
}
-void ISel::emitGEPOperation(Value *Src, User::op_iterator IdxBegin,
+void ISel::emitGEPOperation(MachineBasicBlock *MBB,
+ MachineBasicBlock::iterator &IP,
+ Value *Src, User::op_iterator IdxBegin,
User::op_iterator IdxEnd, unsigned TargetReg) {
const TargetData &TD = TM.getTargetData();
const Type *Ty = Src->getType();
- unsigned basePtrReg = getReg(Src);
+ unsigned basePtrReg = getReg(Src, MBB, IP);
// GEPs have zero or more indices; we must perform a struct access
// or array access for each one.
unsigned memberOffset =
TD.getStructLayout (StTy)->MemberOffsets[idxValue];
// Emit an ADD to add memberOffset to the basePtr.
- BuildMI (BB, X86::ADDri32, 2,
- nextBasePtrReg).addReg (basePtrReg).addZImm (memberOffset);
+ BMI(MBB, IP, X86::ADDri32, 2,
+ nextBasePtrReg).addReg (basePtrReg).addZImm (memberOffset);
// The next type is the member of the structure selected by the
// index.
Ty = StTy->getElementTypes ()[idxValue];
- } else if (const SequentialType *SqTy = cast <SequentialType> (Ty)) {
+ } else if (const SequentialType *SqTy = cast <SequentialType>(Ty)) {
// It's an array or pointer access: [ArraySize x ElementType].
- const Type *typeOfSequentialTypeIndex = SqTy->getIndexType ();
+
// idx is the index into the array. Unlike with structure
// indices, we may not know its actual value at code-generation
// time.
- assert (idx->getType () == typeOfSequentialTypeIndex
- && "Funny-looking array index in GEP");
- // We want to add basePtrReg to (idxReg * sizeof
- // ElementType). First, we must find the size of the pointed-to
- // type. (Not coincidentally, the next type is the type of the
- // elements in the array.)
- Ty = SqTy->getElementType ();
- unsigned elementSize = TD.getTypeSize (Ty);
- unsigned elementSizeReg = makeAnotherReg(Type::UIntTy);
- copyConstantToRegister (ConstantInt::get (typeOfSequentialTypeIndex,
- elementSize),
- elementSizeReg);
- unsigned idxReg = getReg (idx);
- // Emit a MUL to multiply the register holding the index by
- // elementSize, putting the result in memberOffsetReg.
- unsigned memberOffsetReg = makeAnotherReg(Type::UIntTy);
- doMultiply (memberOffsetReg, typeOfSequentialTypeIndex,
- elementSizeReg, idxReg);
- // Emit an ADD to add memberOffsetReg to the basePtr.
- BuildMI (BB, X86::ADDrr32, 2,
- nextBasePtrReg).addReg (basePtrReg).addReg (memberOffsetReg);
+ assert(idx->getType() == Type::LongTy && "Bad GEP array index!");
+
+ // We want to add basePtrReg to (idxReg * sizeof ElementType). First, we
+ // must find the size of the pointed-to type (Not coincidentally, the next
+ // type is the type of the elements in the array).
+ Ty = SqTy->getElementType();
+ unsigned elementSize = TD.getTypeSize(Ty);
+
+ // If idxReg is a constant, we don't need to perform the multiply!
+ if (ConstantSInt *CSI = dyn_cast<ConstantSInt>(idx)) {
+ if (CSI->isNullValue()) {
+ BMI(MBB, IP, X86::MOVrr32, 1, nextBasePtrReg).addReg(basePtrReg);
+ } else {
+ unsigned Offset = elementSize*CSI->getValue();
+
+ BMI(MBB, IP, X86::ADDri32, 2,
+ nextBasePtrReg).addReg(basePtrReg).addZImm(Offset);
+ }
+ } else if (elementSize == 1) {
+ // If the element size is 1, we don't have to multiply, just add
+ unsigned idxReg = getReg(idx, MBB, IP);
+ BMI(MBB, IP, X86::ADDrr32, 2,
+ nextBasePtrReg).addReg(basePtrReg).addReg(idxReg);
+ } else {
+ unsigned idxReg = getReg(idx, MBB, IP);
+ unsigned OffsetReg = makeAnotherReg(Type::UIntTy);
+ if (unsigned Shift = ExactLog2(elementSize)) {
+ // If the element size is exactly a power of 2, use a shift to get it.
+
+ BMI(MBB, IP, X86::SHLir32, 2,
+ OffsetReg).addReg(idxReg).addZImm(Shift-1);
+ } else {
+ // Most general case, emit a multiply...
+ unsigned elementSizeReg = makeAnotherReg(Type::LongTy);
+ BMI(MBB, IP, X86::MOVir32, 1, elementSizeReg).addZImm(elementSize);
+
+ // Emit a MUL to multiply the register holding the index by
+ // elementSize, putting the result in OffsetReg.
+ doMultiply(MBB, IP, OffsetReg, Type::LongTy, idxReg, elementSizeReg);
+ }
+ // Emit an ADD to add OffsetReg to the basePtr.
+ BMI(MBB, IP, X86::ADDrr32, 2,
+ nextBasePtrReg).addReg (basePtrReg).addReg (OffsetReg);
+ }
}
// Now that we are here, further indices refer to subtypes of this
// one, so we don't need to worry about basePtrReg itself, anymore.
// basePtrReg. Move it to the register where we were expected to
// put the answer. A 32-bit move should do it, because we are in
// ILP32 land.
- BuildMI (BB, X86::MOVrr32, 1, TargetReg).addReg (basePtrReg);
+ BMI(MBB, IP, X86::MOVrr32, 1, TargetReg).addReg (basePtrReg);
}
projects / oota-llvm.git / blobdiff