//===-- X86InstrBuilder.h - Functions to aid building x86 insts -*- C++ -*-===//
-//
+//
// The LLVM Compiler Infrastructure
//
-// This file was developed by the LLVM research group and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
//===----------------------------------------------------------------------===//
//
// This file exposes functions that may be used with BuildMI from the
#ifndef X86INSTRBUILDER_H
#define X86INSTRBUILDER_H
+#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/CodeGen/PseudoSourceValue.h"
namespace llvm {
/// X86AddressMode - This struct holds a generalized full x86 address mode.
/// The base register can be a frame index, which will eventually be replaced
-/// with BP or SP and Disp being offsetted accordingly.
-/// FIXME: add support for globals as a new base type.
+/// with BP or SP and Disp being offsetted accordingly. The displacement may
+/// also include the offset of a global value.
struct X86AddressMode {
- enum {
- UnknownBase,
- RegBase,
- FrameIndexBase
- } BaseType;
-
- union {
- unsigned Reg;
- int FrameIndex;
- } Base;
-
- unsigned Scale;
- unsigned IndexReg;
- unsigned Disp;
-
- X86AddressMode() : BaseType(UnknownBase) {}
+ enum {
+ RegBase,
+ FrameIndexBase
+ } BaseType;
+
+ union {
+ unsigned Reg;
+ int FrameIndex;
+ } Base;
+
+ unsigned Scale;
+ unsigned IndexReg;
+ unsigned Disp;
+ GlobalValue *GV;
+ unsigned GVOpFlags;
+
+ X86AddressMode()
+ : BaseType(RegBase), Scale(1), IndexReg(0), Disp(0), GV(0), GVOpFlags(0) {
+ Base.Reg = 0;
+ }
};
/// addDirectMem - This function is used to add a direct memory reference to the
unsigned Reg) {
// Because memory references are always represented with four
// values, this adds: Reg, [1, NoReg, 0] to the instruction.
- return MIB.addReg(Reg).addZImm(1).addReg(0).addSImm(0);
+ return MIB.addReg(Reg).addImm(1).addReg(0).addImm(0);
+}
+
+inline const MachineInstrBuilder &addLeaOffset(const MachineInstrBuilder &MIB,
+ int Offset) {
+ return MIB.addImm(1).addReg(0).addImm(Offset);
}
+inline const MachineInstrBuilder &addOffset(const MachineInstrBuilder &MIB,
+ int Offset) {
+ return addLeaOffset(MIB, Offset).addReg(0);
+}
/// addRegOffset - This function is used to add a memory reference of the form
/// [Reg + Offset], i.e., one with no scale or index, but with a
/// displacement. An example is: DWORD PTR [EAX + 4].
///
inline const MachineInstrBuilder &addRegOffset(const MachineInstrBuilder &MIB,
- unsigned Reg, int Offset) {
- return MIB.addReg(Reg).addZImm(1).addReg(0).addSImm(Offset);
+ unsigned Reg, bool isKill,
+ int Offset) {
+ return addOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset);
}
-inline const MachineInstrBuilder &addFullAddress(const MachineInstrBuilder &MIB,
- const X86AddressMode &AM) {
+inline const MachineInstrBuilder &addLeaRegOffset(const MachineInstrBuilder &MIB,
+ unsigned Reg, bool isKill,
+ int Offset) {
+ return addLeaOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset);
+}
+
+/// addRegReg - This function is used to add a memory reference of the form:
+/// [Reg + Reg].
+inline const MachineInstrBuilder &addRegReg(const MachineInstrBuilder &MIB,
+ unsigned Reg1, bool isKill1,
+ unsigned Reg2, bool isKill2) {
+ return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(1)
+ .addReg(Reg2, getKillRegState(isKill2)).addImm(0);
+}
+
+inline const MachineInstrBuilder &addLeaAddress(const MachineInstrBuilder &MIB,
+ const X86AddressMode &AM) {
assert (AM.Scale == 1 || AM.Scale == 2 || AM.Scale == 4 || AM.Scale == 8);
if (AM.BaseType == X86AddressMode::RegBase)
MIB.addFrameIndex(AM.Base.FrameIndex);
else
assert (0);
- return MIB.addZImm(AM.Scale).addReg(AM.IndexReg).addSImm(AM.Disp);
+ MIB.addImm(AM.Scale).addReg(AM.IndexReg);
+ if (AM.GV)
+ return MIB.addGlobalAddress(AM.GV, AM.Disp, AM.GVOpFlags);
+ else
+ return MIB.addImm(AM.Disp);
+}
+
+inline const MachineInstrBuilder &addFullAddress(const MachineInstrBuilder &MIB,
+ const X86AddressMode &AM) {
+ return addLeaAddress(MIB, AM).addReg(0);
}
/// addFrameReference - This function is used to add a reference to the base of
///
inline const MachineInstrBuilder &
addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset = 0) {
- return MIB.addFrameIndex(FI).addZImm(1).addReg(0).addSImm(Offset);
+ MachineInstr *MI = MIB;
+ MachineFunction &MF = *MI->getParent()->getParent();
+ MachineFrameInfo &MFI = *MF.getFrameInfo();
+ const TargetInstrDesc &TID = MI->getDesc();
+ unsigned Flags = 0;
+ if (TID.mayLoad())
+ Flags |= MachineMemOperand::MOLoad;
+ if (TID.mayStore())
+ Flags |= MachineMemOperand::MOStore;
+ MachineMemOperand MMO(PseudoSourceValue::getFixedStack(FI),
+ Flags,
+ MFI.getObjectOffset(FI) + Offset,
+ MFI.getObjectSize(FI),
+ MFI.getObjectAlignment(FI));
+ return addOffset(MIB.addFrameIndex(FI), Offset)
+ .addMemOperand(MMO);
}
/// addConstantPoolReference - This function is used to add a reference to the
/// base of a constant value spilled to the per-function constant pool. The
-/// reference has base register ConstantPoolIndex offset which is retained until
-/// either machine code emission or assembly output. This allows an optional
-/// offset to be added as well.
+/// reference uses the abstract ConstantPoolIndex which is retained until
+/// either machine code emission or assembly output. In PIC mode on x86-32,
+/// the GlobalBaseReg parameter can be used to make this a
+/// GlobalBaseReg-relative reference.
///
inline const MachineInstrBuilder &
addConstantPoolReference(const MachineInstrBuilder &MIB, unsigned CPI,
- int Offset = 0) {
- return MIB.addConstantPoolIndex(CPI).addZImm(1).addReg(0).addSImm(Offset);
+ unsigned GlobalBaseReg, unsigned char OpFlags) {
+ //FIXME: factor this
+ return MIB.addReg(GlobalBaseReg).addImm(1).addReg(0)
+ .addConstantPoolIndex(CPI, 0, OpFlags).addReg(0);
}
} // End llvm namespace
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