Lowers block address. Currently asserts when relocation model is not PIC. Patch by...

[oota-llvm.git] / lib / Target / X86 / X86InstrExtension.td

diff --git a/lib/Target/X86/X86InstrExtension.td b/lib/Target/X86/X86InstrExtension.td
index a077fcea4b339e07de53c2dff65a0ac9a4f3c93a..867c0f8b68480c10018088aa973eb16816eb6ce8 100644 (file)
--- a/lib/Target/X86/X86InstrExtension.td
+++ b/lib/Target/X86/X86InstrExtension.td
@@ -98,12 +98,12 @@ def MOVZX32rm16: I<0xB7, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
 // instead of GR32. This allows them to operate on h registers on x86-64.
 def MOVZX32_NOREXrr8 : I<0xB6, MRMSrcReg,
                          (outs GR32_NOREX:$dst), (ins GR8:$src),
-                         "movz{bl|x}\t{$src, $dst|$dst, $src}  # NOREX",
+                         "movz{bl|x}\t{$src, $dst|$dst, $src}",
                          []>, TB;
 let mayLoad = 1 in
 def MOVZX32_NOREXrm8 : I<0xB6, MRMSrcMem,
                          (outs GR32_NOREX:$dst), (ins i8mem:$src),
-                         "movz{bl|x}\t{$src, $dst|$dst, $src}  # NOREX",
+                         "movz{bl|x}\t{$src, $dst|$dst, $src}",
                          []>, TB;
 
 // MOVSX64rr8 always has a REX prefix and it has an 8-bit register