Turn off the old way of handling debug information in the code generator. Use

[oota-llvm.git] / lib / Target / X86 / X86InstrFPStack.td

diff --git a/lib/Target/X86/X86InstrFPStack.td b/lib/Target/X86/X86InstrFPStack.td
index be9129471ccfd993ef70d132ab8054e08dd23b5f..bc7def457c0f163e690a9eaf0297e7b72dc2c4ef 100644 (file)
--- a/lib/Target/X86/X86InstrFPStack.td
+++ b/lib/Target/X86/X86InstrFPStack.td
@@ -72,45 +72,45 @@ def fpimmneg1 : PatLeaf<(fpimm), [{
 let usesCustomDAGSchedInserter = 1 in {  // Expanded by the scheduler.
   def FP32_TO_INT16_IN_MEM : I<0, Pseudo,
                               (outs), (ins i16mem:$dst, RFP32:$src),
-                              "#FP32_TO_INT16_IN_MEM PSEUDO!",
+                              "##FP32_TO_INT16_IN_MEM PSEUDO!",
                               [(X86fp_to_i16mem RFP32:$src, addr:$dst)]>;
   def FP32_TO_INT32_IN_MEM : I<0, Pseudo,
                               (outs), (ins i32mem:$dst, RFP32:$src),
-                              "#FP32_TO_INT32_IN_MEM PSEUDO!",
+                              "##FP32_TO_INT32_IN_MEM PSEUDO!",
                               [(X86fp_to_i32mem RFP32:$src, addr:$dst)]>;
   def FP32_TO_INT64_IN_MEM : I<0, Pseudo,
                               (outs), (ins i64mem:$dst, RFP32:$src),
-                              "#FP32_TO_INT64_IN_MEM PSEUDO!",
+                              "##FP32_TO_INT64_IN_MEM PSEUDO!",
                               [(X86fp_to_i64mem RFP32:$src, addr:$dst)]>;
   def FP64_TO_INT16_IN_MEM : I<0, Pseudo,
                               (outs), (ins i16mem:$dst, RFP64:$src),
-                              "#FP64_TO_INT16_IN_MEM PSEUDO!",
+                              "##FP64_TO_INT16_IN_MEM PSEUDO!",
                               [(X86fp_to_i16mem RFP64:$src, addr:$dst)]>;
   def FP64_TO_INT32_IN_MEM : I<0, Pseudo,
                               (outs), (ins i32mem:$dst, RFP64:$src),
-                              "#FP64_TO_INT32_IN_MEM PSEUDO!",
+                              "##FP64_TO_INT32_IN_MEM PSEUDO!",
                               [(X86fp_to_i32mem RFP64:$src, addr:$dst)]>;
   def FP64_TO_INT64_IN_MEM : I<0, Pseudo,
                               (outs), (ins i64mem:$dst, RFP64:$src),
-                              "#FP64_TO_INT64_IN_MEM PSEUDO!",
+                              "##FP64_TO_INT64_IN_MEM PSEUDO!",
                               [(X86fp_to_i64mem RFP64:$src, addr:$dst)]>;
   def FP80_TO_INT16_IN_MEM : I<0, Pseudo,
                               (outs), (ins i16mem:$dst, RFP80:$src),
-                              "#FP80_TO_INT16_IN_MEM PSEUDO!",
+                              "##FP80_TO_INT16_IN_MEM PSEUDO!",
                               [(X86fp_to_i16mem RFP80:$src, addr:$dst)]>;
   def FP80_TO_INT32_IN_MEM : I<0, Pseudo,
                               (outs), (ins i32mem:$dst, RFP80:$src),
-                              "#FP80_TO_INT32_IN_MEM PSEUDO!",
+                              "##FP80_TO_INT32_IN_MEM PSEUDO!",
                               [(X86fp_to_i32mem RFP80:$src, addr:$dst)]>;
   def FP80_TO_INT64_IN_MEM : I<0, Pseudo,
                               (outs), (ins i64mem:$dst, RFP80:$src),
-                              "#FP80_TO_INT64_IN_MEM PSEUDO!",
+                              "##FP80_TO_INT64_IN_MEM PSEUDO!",
                               [(X86fp_to_i64mem RFP80:$src, addr:$dst)]>;
 }
 
 let isTerminator = 1 in
   let Defs = [FP0, FP1, FP2, FP3, FP4, FP5, FP6] in
-    def FP_REG_KILL  : I<0, Pseudo, (outs), (ins), "#FP_REG_KILL", []>;
+    def FP_REG_KILL  : I<0, Pseudo, (outs), (ins), "##FP_REG_KILL", []>;
 
 // All FP Stack operations are represented with four instructions here.  The
 // first three instructions, generated by the instruction selector, use "RFP32"
@@ -145,16 +145,18 @@ def FpGET_ST1_32 : FpI_<(outs RFP32:$dst), (ins), SpecialFP, []>; // FPR = ST(1)
 def FpGET_ST1_64 : FpI_<(outs RFP64:$dst), (ins), SpecialFP, []>; // FPR = ST(1)
 def FpGET_ST1_80 : FpI_<(outs RFP80:$dst), (ins), SpecialFP, []>; // FPR = ST(1)
 
-def FpGET_ST0_ST1 : FpI_<(outs RFP80:$dst1, RFP80:$dst2), (ins), SpecialFP,
-                         []>;                        // FPR = ST(0), FPR = ST(1)
-
-
 let Defs = [ST0] in {
 def FpSET_ST0_32 : FpI_<(outs), (ins RFP32:$src), SpecialFP, []>; // ST(0) = FPR
 def FpSET_ST0_64 : FpI_<(outs), (ins RFP64:$src), SpecialFP, []>; // ST(0) = FPR
 def FpSET_ST0_80 : FpI_<(outs), (ins RFP80:$src), SpecialFP, []>; // ST(0) = FPR
 }
 
+let Defs = [ST1] in {
+def FpSET_ST1_32 : FpI_<(outs), (ins RFP32:$src), SpecialFP, []>; // ST(1) = FPR
+def FpSET_ST1_64 : FpI_<(outs), (ins RFP64:$src), SpecialFP, []>; // ST(1) = FPR
+def FpSET_ST1_80 : FpI_<(outs), (ins RFP80:$src), SpecialFP, []>; // ST(1) = FPR
+}
+
 // FpIf32, FpIf64 - Floating Point Psuedo Instruction template.
 // f32 instructions can use SSE1 and are predicated on FPStackf32 == !SSE1.
 // f64 instructions can use SSE2 and are predicated on FPStackf64 == !SSE2.
@@ -346,7 +348,7 @@ def CMOVNP_F : FPI<0xD8, AddRegFrm, (outs RST:$op), (ins),
                   "fcmovnu\t{$op, %st(0)|%ST(0), $op}">, DB;
 
 // Floating point loads & stores.
-let isSimpleLoad = 1 in {
+let canFoldAsLoad = 1 in {
 def LD_Fp32m   : FpIf32<(outs RFP32:$dst), (ins f32mem:$src), ZeroArgFP,
                   [(set RFP32:$dst, (loadf32 addr:$src))]>;
 let isReMaterializable = 1, mayHaveSideEffects = 1 in