Update the .cvs files.

[oota-llvm.git] / lib / Target / X86 / X86InstrFormats.td

diff --git a/lib/Target/X86/X86InstrFormats.td b/lib/Target/X86/X86InstrFormats.td
index 86a327d64fc713b115883a0f319966573736a327..8d098f12ae2249ecde10d90533260a3ac0fbe511 100644 (file)
--- a/lib/Target/X86/X86InstrFormats.td
+++ b/lib/Target/X86/X86InstrFormats.td
@@ -62,6 +62,7 @@ def SpecialFP  : FPFormat<7>;
 class OpSize { bit hasOpSizePrefix = 1; }
 class AdSize { bit hasAdSizePrefix = 1; }
 class REX_W  { bit hasREX_WPrefix = 1; }
+class LOCK   { bit hasLockPrefix = 1; }
 class TB     { bits<4> Prefix = 1; }
 class REP    { bits<4> Prefix = 2; }
 class D8     { bits<4> Prefix = 3; }
@@ -102,6 +103,7 @@ class X86Inst<bits<8> opcod, Format f, ImmType i, dag outs, dag ins,
   bit hasREX_WPrefix  = 0;  // Does this inst requires the REX.W prefix?
   FPFormat FPForm;          // What flavor of FP instruction is this?
   bits<3> FPFormBits = 0;
+  bit hasLockPrefix = 0;  // Does this inst have a 0xF0 prefix?
 }
 
 class I<bits<8> o, Format f, dag outs, dag ins, string asm, list<dag> pattern>
@@ -204,14 +206,14 @@ class SS3AI<bits<8> o, Format F, dag outs, dag ins, string asm,
 // SSE4.1 Instruction Templates:
 // 
 //   SS48I - SSE 4.1 instructions with T8 prefix.
-//   SS41AI - SSE 4.1 instructions with TA prefix.
+//   SS41AIi8 - SSE 4.1 instructions with TA prefix and ImmT == Imm8.
 //
 class SS48I<bits<8> o, Format F, dag outs, dag ins, string asm,
             list<dag> pattern>
       : I<o, F, outs, ins, asm, pattern>, T8, Requires<[HasSSE41]>;
-class SS4AI<bits<8> o, Format F, dag outs, dag ins, string asm,
+class SS4AIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
             list<dag> pattern>
-      : I<o, F, outs, ins, asm, pattern>, TA, Requires<[HasSSE41]>;
+      : Ii8<o, F, outs, ins, asm, pattern>, TA, Requires<[HasSSE41]>;
 
 
 // X86-64 Instruction templates...