// Format specifies the encoding used by the instruction. This is part of the
// ad-hoc solution used to emit machine instruction encodings by our machine
// code emitter.
-class Format<bits<6> val> {
- bits<6> Value = val;
+class Format<bits<7> val> {
+ bits<7> Value = val;
}
def Pseudo : Format<0>; def RawFrm : Format<1>;
def MRM0m : Format<24>; def MRM1m : Format<25>; def MRM2m : Format<26>;
def MRM3m : Format<27>; def MRM4m : Format<28>; def MRM5m : Format<29>;
def MRM6m : Format<30>; def MRM7m : Format<31>;
-def MRM_C0 : Format<32>;
-def MRM_C1 : Format<33>;
-def MRM_C2 : Format<34>;
-def MRM_C3 : Format<35>;
-def MRM_C4 : Format<36>;
-def MRM_C8 : Format<37>;
-def MRM_C9 : Format<38>;
-def MRM_CA : Format<39>;
-def MRM_CB : Format<40>;
-def MRM_D0 : Format<41>;
-def MRM_D1 : Format<42>;
-def MRM_D4 : Format<43>;
-def MRM_D5 : Format<44>;
-def MRM_D6 : Format<45>;
-def MRM_D8 : Format<46>;
-def MRM_D9 : Format<47>;
-def MRM_DA : Format<48>;
-def MRM_DB : Format<49>;
-def MRM_DC : Format<50>;
-def MRM_DD : Format<51>;
-def MRM_DE : Format<52>;
-def MRM_DF : Format<53>;
-def MRM_E0 : Format<54>;
-def MRM_E8 : Format<55>;
-def MRM_F0 : Format<56>;
-def MRM_F8 : Format<57>;
-def MRM_F9 : Format<58>;
+def MRM_C0 : Format<32>; def MRM_C1 : Format<33>; def MRM_C2 : Format<34>;
+def MRM_C3 : Format<35>; def MRM_C4 : Format<36>; def MRM_C8 : Format<37>;
+def MRM_C9 : Format<38>; def MRM_CA : Format<39>; def MRM_CB : Format<40>;
+def MRM_D0 : Format<41>; def MRM_D1 : Format<42>; def MRM_D4 : Format<43>;
+def MRM_D5 : Format<44>; def MRM_D6 : Format<45>; def MRM_D8 : Format<46>;
+def MRM_D9 : Format<47>; def MRM_DA : Format<48>; def MRM_DB : Format<49>;
+def MRM_DC : Format<50>; def MRM_DD : Format<51>; def MRM_DE : Format<52>;
+def MRM_DF : Format<53>; def MRM_E0 : Format<54>; def MRM_E1 : Format<55>;
+def MRM_E2 : Format<56>; def MRM_E3 : Format<57>; def MRM_E4 : Format<58>;
+def MRM_E5 : Format<59>; def MRM_E8 : Format<60>; def MRM_E9 : Format<61>;
+def MRM_EA : Format<62>; def MRM_EB : Format<63>; def MRM_EC : Format<64>;
+def MRM_ED : Format<65>; def MRM_EE : Format<66>; def MRM_F0 : Format<67>;
+def MRM_F1 : Format<68>; def MRM_F2 : Format<69>; def MRM_F3 : Format<70>;
+def MRM_F4 : Format<71>; def MRM_F5 : Format<72>; def MRM_F6 : Format<73>;
+def MRM_F7 : Format<74>; def MRM_F8 : Format<75>; def MRM_F9 : Format<76>;
+def MRM_FA : Format<77>; def MRM_FB : Format<78>; def MRM_FC : Format<79>;
+def MRM_FD : Format<80>; def MRM_FE : Format<81>; def MRM_FF : Format<82>;
// ImmType - This specifies the immediate type used by an instruction. This is
// part of the ad-hoc solution used to emit machine instruction encodings by our
def XD : Prefix<4>;
// Class specifying the opcode map.
-class Map<bits<5> val> {
- bits<5> Value = val;
+class Map<bits<3> val> {
+ bits<3> Value = val;
}
def OB : Map<0>;
def TB : Map<1>;
def XOP8 : Map<4>;
def XOP9 : Map<5>;
def XOPA : Map<6>;
-def D8 : Map<7>;
-def D9 : Map<8>;
-def DA : Map<9>;
-def DB : Map<10>;
-def DC : Map<11>;
-def DD : Map<12>;
-def DE : Map<13>;
-def DF : Map<14>;
// Class specifying the encoding
class Encoding<bits<2> val> {
class LOCK { bit hasLockPrefix = 1; }
class REP { bit hasREPPrefix = 1; }
class TB { Map OpMap = TB; }
-class D8 { Map OpMap = D8; }
-class D9 { Map OpMap = D9; }
-class DA { Map OpMap = DA; }
-class DB { Map OpMap = DB; }
-class DC { Map OpMap = DC; }
-class DD { Map OpMap = DD; }
-class DE { Map OpMap = DE; }
-class DF { Map OpMap = DF; }
class T8 { Map OpMap = T8; }
class TA { Map OpMap = TA; }
class XOP8 { Map OpMap = XOP8; Prefix OpPrefix = PS; }
class XOP9 { Map OpMap = XOP9; Prefix OpPrefix = PS; }
class XOPA { Map OpMap = XOPA; Prefix OpPrefix = PS; }
+class OBXS { Prefix OpPrefix = XS; }
class PS : TB { Prefix OpPrefix = PS; }
class PD : TB { Prefix OpPrefix = PD; }
class XD : TB { Prefix OpPrefix = XD; }
bits<8> Opcode = opcod;
Format Form = f;
- bits<6> FormBits = Form.Value;
+ bits<7> FormBits = Form.Value;
ImmType ImmT = i;
dag OutOperandList = outs;
OperandSize OpSize = OpSizeFixed; // Does this instruction's encoding change
// based on operand size of the mode
+ bits<2> OpSizeBits = OpSize.Value;
bit hasAdSizePrefix = 0; // Does this inst have a 0x67 prefix?
Prefix OpPrefix = NoPrfx; // Which prefix byte does this inst have?
+ bits<3> OpPrefixBits = OpPrefix.Value;
Map OpMap = OB; // Which opcode map does this inst have?
+ bits<3> OpMapBits = OpMap.Value;
bit hasREX_WPrefix = 0; // Does this inst require the REX.W prefix?
FPFormat FPForm = NotFP; // What flavor of FP instruction is this?
bit hasLockPrefix = 0; // Does this inst have a 0xF0 prefix?
Domain ExeDomain = d;
bit hasREPPrefix = 0; // Does this inst have a REP prefix?
Encoding OpEnc = EncNormal; // Encoding used by this instruction
+ bits<2> OpEncBits = OpEnc.Value;
bit hasVEX_WPrefix = 0; // Does this inst set the VEX_W field?
bit hasVEX_4V = 0; // Does this inst require the VEX.VVVV field?
bit hasVEX_4VOp3 = 0; // Does this inst require the VEX.VVVV field to
bit hasEVEX_RC = 0; // Explicitly specified rounding control in FP instruction.
// TSFlags layout should be kept in sync with X86InstrInfo.h.
- let TSFlags{5-0} = FormBits;
- let TSFlags{7-6} = OpSize.Value;
- let TSFlags{8} = hasAdSizePrefix;
- let TSFlags{11-9} = OpPrefix.Value;
- let TSFlags{16-12} = OpMap.Value;
- let TSFlags{17} = hasREX_WPrefix;
- let TSFlags{21-18} = ImmT.Value;
- let TSFlags{24-22} = FPForm.Value;
- let TSFlags{25} = hasLockPrefix;
- let TSFlags{26} = hasREPPrefix;
- let TSFlags{28-27} = ExeDomain.Value;
- let TSFlags{30-29} = OpEnc.Value;
- let TSFlags{38-31} = Opcode;
- let TSFlags{39} = hasVEX_WPrefix;
- let TSFlags{40} = hasVEX_4V;
- let TSFlags{41} = hasVEX_4VOp3;
- let TSFlags{42} = hasVEX_i8ImmReg;
- let TSFlags{43} = hasVEX_L;
- let TSFlags{44} = ignoresVEX_L;
- let TSFlags{45} = hasEVEX_K;
- let TSFlags{46} = hasEVEX_Z;
- let TSFlags{47} = hasEVEX_L2;
- let TSFlags{48} = hasEVEX_B;
- let TSFlags{50-49} = EVEX_CD8E;
- let TSFlags{53-51} = EVEX_CD8V;
- let TSFlags{54} = has3DNow0F0FOpcode;
- let TSFlags{55} = hasMemOp4Prefix;
- let TSFlags{56} = hasEVEX_RC;
+ let TSFlags{6-0} = FormBits;
+ let TSFlags{8-7} = OpSizeBits;
+ let TSFlags{9} = hasAdSizePrefix;
+ let TSFlags{12-10} = OpPrefixBits;
+ let TSFlags{15-13} = OpMapBits;
+ let TSFlags{16} = hasREX_WPrefix;
+ let TSFlags{20-17} = ImmT.Value;
+ let TSFlags{23-21} = FPForm.Value;
+ let TSFlags{24} = hasLockPrefix;
+ let TSFlags{25} = hasREPPrefix;
+ let TSFlags{27-26} = ExeDomain.Value;
+ let TSFlags{29-28} = OpEncBits;
+ let TSFlags{37-30} = Opcode;
+ let TSFlags{38} = hasVEX_WPrefix;
+ let TSFlags{39} = hasVEX_4V;
+ let TSFlags{40} = hasVEX_4VOp3;
+ let TSFlags{41} = hasVEX_i8ImmReg;
+ let TSFlags{42} = hasVEX_L;
+ let TSFlags{43} = ignoresVEX_L;
+ let TSFlags{44} = hasEVEX_K;
+ let TSFlags{45} = hasEVEX_Z;
+ let TSFlags{46} = hasEVEX_L2;
+ let TSFlags{47} = hasEVEX_B;
+ let TSFlags{49-48} = EVEX_CD8E;
+ let TSFlags{52-50} = EVEX_CD8V;
+ let TSFlags{53} = has3DNow0F0FOpcode;
+ let TSFlags{54} = hasMemOp4Prefix;
+ let TSFlags{55} = hasEVEX_RC;
}
class PseudoI<dag oops, dag iops, list<dag> pattern>
let CodeSize = 3;
}
-class RSSI<bits<8> o, Format F, dag outs, dag ins, string asm,
- list<dag> pattern, InstrItinClass itin = NoItinerary>
- : SSI<o, F, outs, ins, asm, pattern, itin>, REX_W;
-class RSDI<bits<8> o, Format F, dag outs, dag ins, string asm,
- list<dag> pattern, InstrItinClass itin = NoItinerary>
- : SDI<o, F, outs, ins, asm, pattern, itin>, REX_W;
-class RPDI<bits<8> o, Format F, dag outs, dag ins, string asm,
- list<dag> pattern, InstrItinClass itin = NoItinerary>
- : PDI<o, F, outs, ins, asm, pattern, itin>, REX_W;
-class VRPDI<bits<8> o, Format F, dag outs, dag ins, string asm,
- list<dag> pattern, InstrItinClass itin = NoItinerary>
- : VPDI<o, F, outs, ins, asm, pattern, itin>, VEX_W;
class RS2I<bits<8> o, Format F, dag outs, dag ins, string asm,
list<dag> pattern, InstrItinClass itin = NoItinerary>
: S2I<o, F, outs, ins, asm, pattern, itin>, REX_W;
projects / oota-llvm.git / blobdiff