- Renamed AddedCost to AddedComplexity.

[oota-llvm.git] / lib / Target / X86 / X86InstrInfo.cpp

diff --git a/lib/Target/X86/X86InstrInfo.cpp b/lib/Target/X86/X86InstrInfo.cpp
index 20e1cd0ecd7bc77319912609f43b7d1d6def5c7c..31a4f6fe2e7e7f87e436ce0ddb9b0effbf0594d2 100644 (file)
--- a/lib/Target/X86/X86InstrInfo.cpp
+++ b/lib/Target/X86/X86InstrInfo.cpp
@@ -31,8 +31,10 @@ bool X86InstrInfo::isMoveInstr(const MachineInstr& MI,
       oc == X86::FpMOV  || oc == X86::MOVSSrr || oc == X86::MOVSDrr ||
       oc == X86::FsMOVAPSrr || oc == X86::FsMOVAPDrr ||
       oc == X86::MOVAPSrr || oc == X86::MOVAPDrr ||
-      oc == X86::MOVSS128rr || oc == X86::MOVSD128rr ||
-      oc == X86::MOVD128rr || oc == X86::MOVQ128rr) {
+      oc == X86::MOVSS2PSrr || oc == X86::MOVSD2PDrr ||
+      oc == X86::MOVPS2SSrr || oc == X86::MOVPD2SDrr ||
+      oc == X86::MOVDI2PDIrr || oc == X86::MOVQI2PQIrr ||
+      oc == X86::MOVPDI2DIrr) {
       assert(MI.getNumOperands() == 2 &&
              MI.getOperand(0).isRegister() &&
              MI.getOperand(1).isRegister() &&
@@ -54,6 +56,8 @@ unsigned X86InstrInfo::isLoadFromStackSlot(MachineInstr *MI,
   case X86::FpLD64m:
   case X86::MOVSSrm:
   case X86::MOVSDrm:
+  case X86::MOVAPSrm:
+  case X86::MOVAPDrm:
     if (MI->getOperand(1).isFrameIndex() && MI->getOperand(2).isImmediate() &&
         MI->getOperand(3).isRegister() && MI->getOperand(4).isImmediate() &&
         MI->getOperand(2).getImmedValue() == 1 &&
@@ -77,6 +81,8 @@ unsigned X86InstrInfo::isStoreToStackSlot(MachineInstr *MI,
   case X86::FpSTP64m:
   case X86::MOVSSmr:
   case X86::MOVSDmr:
+  case X86::MOVAPSmr:
+  case X86::MOVAPDmr:
     if (MI->getOperand(0).isFrameIndex() && MI->getOperand(1).isImmediate() &&
         MI->getOperand(2).isRegister() && MI->getOperand(3).isImmediate() &&
         MI->getOperand(1).getImmedValue() == 1 &&