Change Library Names Not To Conflict With Others When Installed

[oota-llvm.git] / lib / Target / X86 / X86InstrInfo.cpp

diff --git a/lib/Target/X86/X86InstrInfo.cpp b/lib/Target/X86/X86InstrInfo.cpp
index 298af02d8aec2752d12d4e1c9ec35488cf881d2d..42b0ec95a87647b51320724c5f25bc8e85449d17 100644 (file)
--- a/lib/Target/X86/X86InstrInfo.cpp
+++ b/lib/Target/X86/X86InstrInfo.cpp
@@ -14,56 +14,57 @@
 #include "X86InstrInfo.h"
 #include "X86.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
-
 #include "X86GenInstrInfo.inc"
-
 using namespace llvm;
 
 X86InstrInfo::X86InstrInfo()
-  : TargetInstrInfo(X86Insts, sizeof(X86Insts)/sizeof(X86Insts[0]), 0) {
+  : TargetInstrInfo(X86Insts, sizeof(X86Insts)/sizeof(X86Insts[0])) {
 }
 
 
-// createNOPinstr - returns the target's implementation of NOP, which is
-// usually a pseudo-instruction, implemented by a degenerate version of
-// another instruction, e.g. X86: `xchg ax, ax'; SparcV9: `sethi r0, r0, r0'
-//
-MachineInstr* X86InstrInfo::createNOPinstr() const {
-  return BuildMI(X86::XCHGrr16, 2).addReg(X86::AX, MOTy::UseAndDef)
-                                  .addReg(X86::AX, MOTy::UseAndDef);
-}
-
-
-/// isNOPinstr - not having a special NOP opcode, we need to know if a given
-/// instruction is interpreted as an `official' NOP instr, i.e., there may be
-/// more than one way to `do nothing' but only one canonical way to slack off.
-//
-bool X86InstrInfo::isNOPinstr(const MachineInstr &MI) const {
-  // Make sure the instruction is EXACTLY `xchg ax, ax'
-  if (MI.getOpcode() == X86::XCHGrr16) {
-    const MachineOperand &op0 = MI.getOperand(0), &op1 = MI.getOperand(1);
-    if (op0.isRegister() && op0.getReg() == X86::AX &&
-        op1.isRegister() && op1.getReg() == X86::AX) {
-      return true;
-    }
-  }
-  // FIXME: there are several NOOP instructions, we should check for them here.
-  return false;
-}
-
 bool X86InstrInfo::isMoveInstr(const MachineInstr& MI,
                                unsigned& sourceReg,
                                unsigned& destReg) const {
   MachineOpCode oc = MI.getOpcode();
-  if (oc == X86::MOVrr8 || oc == X86::MOVrr16 || oc == X86::MOVrr32 ||
+  if (oc == X86::MOV8rr || oc == X86::MOV16rr || oc == X86::MOV32rr ||
       oc == X86::FpMOV) {
       assert(MI.getNumOperands() == 2 &&
              MI.getOperand(0).isRegister() &&
              MI.getOperand(1).isRegister() &&
              "invalid register-register move instruction");
-      sourceReg = MI.getOperand(1).getAllocatedRegNum();
-      destReg = MI.getOperand(0).getAllocatedRegNum();
+      sourceReg = MI.getOperand(1).getReg();
+      destReg = MI.getOperand(0).getReg();
       return true;
   }
   return false;
 }
+
+void X86InstrInfo::insertGoto(MachineBasicBlock& MBB,
+                              MachineBasicBlock& TMBB) const {
+  BuildMI(MBB, MBB.end(), X86::JMP, 1).addMBB(&TMBB);
+}
+
+MachineBasicBlock::iterator
+X86InstrInfo::reverseBranchCondition(MachineBasicBlock::iterator MI) const {
+  unsigned Opcode = MI->getOpcode();
+  assert(isBranch(Opcode) && "MachineInstr must be a branch");
+  unsigned ROpcode;
+  switch (Opcode) {
+  default: assert(0 && "Cannot reverse unconditional branches!");
+  case X86::JB:  ROpcode = X86::JAE; break;
+  case X86::JAE: ROpcode = X86::JB;  break;
+  case X86::JE:  ROpcode = X86::JNE; break;
+  case X86::JNE: ROpcode = X86::JE;  break;
+  case X86::JBE: ROpcode = X86::JA;  break;
+  case X86::JA:  ROpcode = X86::JBE; break;
+  case X86::JS:  ROpcode = X86::JNS; break;
+  case X86::JNS: ROpcode = X86::JS;  break;
+  case X86::JL:  ROpcode = X86::JGE; break;
+  case X86::JGE: ROpcode = X86::JL;  break;
+  case X86::JLE: ROpcode = X86::JG;  break;
+  case X86::JG:  ROpcode = X86::JLE; break;
+  }
+  MachineBasicBlock* MBB = MI->getParent();
+  MachineBasicBlock* TMBB = MI->getOperand(0).getMachineBasicBlock();
+  return BuildMI(*MBB, MBB->erase(MI), ROpcode, 1).addMBB(TMBB);
+}