Resolve BB references with relocation.

[oota-llvm.git] / lib / Target / X86 / X86InstrInfo.cpp

diff --git a/lib/Target/X86/X86InstrInfo.cpp b/lib/Target/X86/X86InstrInfo.cpp
index dec8620fd73c5e1c645e8a295787adcb47ef616d..47388eae48363b7ca5054fd93b1df1da9467c13c 100644 (file)
--- a/lib/Target/X86/X86InstrInfo.cpp
+++ b/lib/Target/X86/X86InstrInfo.cpp
@@ -13,13 +13,16 @@
 
 #include "X86InstrInfo.h"
 #include "X86.h"
+#include "X86GenInstrInfo.inc"
 #include "X86InstrBuilder.h"
+#include "X86Subtarget.h"
+#include "X86TargetMachine.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
-#include "X86GenInstrInfo.inc"
 using namespace llvm;
 
-X86InstrInfo::X86InstrInfo()
-  : TargetInstrInfo(X86Insts, sizeof(X86Insts)/sizeof(X86Insts[0])) {
+X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
+  : TargetInstrInfo(X86Insts, sizeof(X86Insts)/sizeof(X86Insts[0])),
+    TM(tm) {
 }
 
 
@@ -28,8 +31,14 @@ bool X86InstrInfo::isMoveInstr(const MachineInstr& MI,
                                unsigned& destReg) const {
   MachineOpCode oc = MI.getOpcode();
   if (oc == X86::MOV8rr || oc == X86::MOV16rr || oc == X86::MOV32rr ||
+      oc == X86::MOV16to16_ || oc == X86::MOV32to32_ ||
       oc == X86::FpMOV  || oc == X86::MOVSSrr || oc == X86::MOVSDrr ||
-      oc == X86::MOVAPSrr || oc == X86::MOVAPDrr) {
+      oc == X86::FsMOVAPSrr || oc == X86::FsMOVAPDrr ||
+      oc == X86::MOVAPSrr || oc == X86::MOVAPDrr ||
+      oc == X86::MOVSS2PSrr || oc == X86::MOVSD2PDrr ||
+      oc == X86::MOVPS2SSrr || oc == X86::MOVPD2SDrr ||
+      oc == X86::MOVDI2PDIrr || oc == X86::MOVQI2PQIrr ||
+      oc == X86::MOVPDI2DIrr) {
       assert(MI.getNumOperands() == 2 &&
              MI.getOperand(0).isRegister() &&
              MI.getOperand(1).isRegister() &&
@@ -47,10 +56,14 @@ unsigned X86InstrInfo::isLoadFromStackSlot(MachineInstr *MI,
   default: break;
   case X86::MOV8rm:
   case X86::MOV16rm:
+  case X86::MOV16_rm:
   case X86::MOV32rm:
+  case X86::MOV32_rm:
   case X86::FpLD64m:
   case X86::MOVSSrm:
   case X86::MOVSDrm:
+  case X86::MOVAPSrm:
+  case X86::MOVAPDrm:
     if (MI->getOperand(1).isFrameIndex() && MI->getOperand(2).isImmediate() &&
         MI->getOperand(3).isRegister() && MI->getOperand(4).isImmediate() &&
         MI->getOperand(2).getImmedValue() == 1 &&
@@ -70,10 +83,14 @@ unsigned X86InstrInfo::isStoreToStackSlot(MachineInstr *MI,
   default: break;
   case X86::MOV8mr:
   case X86::MOV16mr:
+  case X86::MOV16_mr:
   case X86::MOV32mr:
+  case X86::MOV32_mr:
   case X86::FpSTP64m:
   case X86::MOVSSmr:
   case X86::MOVSDmr:
+  case X86::MOVAPSmr:
+  case X86::MOVAPDmr:
     if (MI->getOperand(0).isFrameIndex() && MI->getOperand(1).isImmediate() &&
         MI->getOperand(2).isRegister() && MI->getOperand(3).isImmediate() &&
         MI->getOperand(1).getImmedValue() == 1 &&
@@ -88,7 +105,6 @@ unsigned X86InstrInfo::isStoreToStackSlot(MachineInstr *MI,
 }
 
 
-
 /// convertToThreeAddress - This method must be implemented by targets that
 /// set the M_CONVERTIBLE_TO_3_ADDR flag.  When this flag is set, the target
 /// may be able to convert a two-address instruction into a true
@@ -104,6 +120,20 @@ MachineInstr *X86InstrInfo::convertToThreeAddress(MachineInstr *MI) const {
   unsigned Dest = MI->getOperand(0).getReg();
   unsigned Src = MI->getOperand(1).getReg();
 
+  switch (MI->getOpcode()) {
+  default: break;
+  case X86::SHUFPSrri: {
+    assert(MI->getNumOperands() == 4 && "Unknown shufps instruction!");
+    const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
+    unsigned A = MI->getOperand(0).getReg();
+    unsigned B = MI->getOperand(1).getReg();
+    unsigned C = MI->getOperand(2).getReg();
+    unsigned M = MI->getOperand(3).getImmedValue();
+    if (!Subtarget->hasSSE2() || B != C) return 0;
+    return BuildMI(X86::PSHUFDri, 2, A).addReg(B).addImm(M);
+  }
+  }
+
   // FIXME: None of these instructions are promotable to LEAs without
   // additional information.  In particular, LEA doesn't set the flags that
   // add and inc do.  :(
@@ -138,12 +168,14 @@ MachineInstr *X86InstrInfo::convertToThreeAddress(MachineInstr *MI) const {
     return addRegReg(BuildMI(X86::LEA16r, 5, Dest), Src,
                      MI->getOperand(2).getReg());
   case X86::ADD32ri:
+  case X86::ADD32ri8:
     assert(MI->getNumOperands() == 3 && "Unknown add instruction!");
     if (MI->getOperand(2).isImmediate())
       return addRegOffset(BuildMI(X86::LEA32r, 5, Dest), Src,
                           MI->getOperand(2).getImmedValue());
     return 0;
   case X86::ADD16ri:
+  case X86::ADD16ri8:
     if (DisableLEA16) return 0;
     assert(MI->getNumOperands() == 3 && "Unknown add instruction!");
     if (MI->getOperand(2).isImmediate())