Fix some warnings, some of which were spurious, and some of which were real

[oota-llvm.git] / lib / Target / X86 / X86InstrInfo.cpp

diff --git a/lib/Target/X86/X86InstrInfo.cpp b/lib/Target/X86/X86InstrInfo.cpp
index 8911562bfc86473465cf6ec4ac42e3ff0e5d41f3..caffe62867b1d1c8d0de3fe86e1ce4155c635c78 100644 (file)
--- a/lib/Target/X86/X86InstrInfo.cpp
+++ b/lib/Target/X86/X86InstrInfo.cpp
@@ -29,8 +29,8 @@ X86InstrInfo::X86InstrInfo()
 // another instruction, e.g. X86: `xchg ax, ax'; SparcV9: `sethi r0, r0, r0'
 //
 MachineInstr* X86InstrInfo::createNOPinstr() const {
-  return BuildMI(X86::XCHGrr16, 2).addReg(X86::AX, MOTy::UseAndDef)
-                                  .addReg(X86::AX, MOTy::UseAndDef);
+  return BuildMI(X86::XCHGrr16, 2).addReg(X86::AX, MachineOperand::UseAndDef)
+                                  .addReg(X86::AX, MachineOperand::UseAndDef);
 }
 
 
@@ -42,8 +42,8 @@ bool X86InstrInfo::isNOPinstr(const MachineInstr &MI) const {
   // Make sure the instruction is EXACTLY `xchg ax, ax'
   if (MI.getOpcode() == X86::XCHGrr16) {
     const MachineOperand &op0 = MI.getOperand(0), &op1 = MI.getOperand(1);
-    if (op0.isPhysicalRegister() && op0.getReg() == X86::AX &&
-        op1.isPhysicalRegister() && op1.getReg() == X86::AX) {
+    if (op0.isRegister() && op0.getReg() == X86::AX &&
+        op1.isRegister() && op1.getReg() == X86::AX) {
       return true;
     }
   }
@@ -61,8 +61,8 @@ bool X86InstrInfo::isMoveInstr(const MachineInstr& MI,
              MI.getOperand(0).isRegister() &&
              MI.getOperand(1).isRegister() &&
              "invalid register-register move instruction");
-      sourceReg = MI.getOperand(1).getAllocatedRegNum();
-      destReg = MI.getOperand(0).getAllocatedRegNum();
+      sourceReg = MI.getOperand(1).getReg();
+      destReg = MI.getOperand(0).getReg();
       return true;
   }
   return false;