// another instruction, e.g. X86: `xchg ax, ax'; SparcV9: `sethi r0, r0, r0'
//
MachineInstr* X86InstrInfo::createNOPinstr() const {
- return BuildMI(X86::XCHGrr16, 2).addReg(X86::AX, MOTy::UseAndDef)
- .addReg(X86::AX, MOTy::UseAndDef);
+ return BuildMI(X86::XCHGrr16, 2).addReg(X86::AX, MachineOperand::UseAndDef)
+ .addReg(X86::AX, MachineOperand::UseAndDef);
}
// Make sure the instruction is EXACTLY `xchg ax, ax'
if (MI.getOpcode() == X86::XCHGrr16) {
const MachineOperand &op0 = MI.getOperand(0), &op1 = MI.getOperand(1);
- if (op0.isMachineRegister() && op0.getMachineRegNum() == X86::AX &&
- op1.isMachineRegister() && op1.getMachineRegNum() == X86::AX) {
+ if (op0.isRegister() && op0.getReg() == X86::AX &&
+ op1.isRegister() && op1.getReg() == X86::AX) {
return true;
}
}
unsigned& sourceReg,
unsigned& destReg) const {
MachineOpCode oc = MI.getOpcode();
- if (oc == X86::MOVrr8 || oc == X86::MOVrr16 || oc == X86::MOVrr32) {
+ if (oc == X86::MOVrr8 || oc == X86::MOVrr16 || oc == X86::MOVrr32 ||
+ oc == X86::FpMOV) {
assert(MI.getNumOperands() == 2 &&
MI.getOperand(0).isRegister() &&
MI.getOperand(1).isRegister() &&
"invalid register-register move instruction");
- sourceReg = MI.getOperand(1).getAllocatedRegNum();
- destReg = MI.getOperand(0).getAllocatedRegNum();
+ sourceReg = MI.getOperand(1).getReg();
+ destReg = MI.getOperand(0).getReg();
return true;
}
return false;