Implement a lot of cast functionality (no FP or 64)

[oota-llvm.git] / lib / Target / X86 / X86InstrInfo.h

diff --git a/lib/Target/X86/X86InstrInfo.h b/lib/Target/X86/X86InstrInfo.h
index 4850d5ee662d490e7210245d4db90c2ab30ba0e5..9d2629120ef0424516fcd2861da5974fdb4c83fc 100644 (file)
--- a/lib/Target/X86/X86InstrInfo.h
+++ b/lib/Target/X86/X86InstrInfo.h
@@ -15,7 +15,82 @@
 ///
 namespace X86II {
   enum {
-    Void        = 1 << 0,  // Set if this instruction produces no value
+    //===------------------------------------------------------------------===//
+    // Instruction types.  These are the standard/most common forms for X86
+    // instructions.
+    //
+
+    /// Raw - This form is for instructions that don't have any operands, so
+    /// they are just a fixed opcode value, like 'leave'.
+    RawFrm         = 0,
+    
+    /// AddRegFrm - This form is used for instructions like 'push r32' that have
+    /// their one register operand added to their opcode.
+    AddRegFrm      = 1,
+
+    /// MRMDestReg - This form is used for instructions that use the Mod/RM byte
+    /// to specify a destination, which in this case is a register.
+    ///
+    MRMDestReg     = 2,
+
+    /// MRMDestMem - This form is used for instructions that use the Mod/RM byte
+    /// to specify a destination, which in this case is memory.
+    ///
+    MRMDestMem     = 3,
+
+    /// MRMSrcReg - This form is used for instructions that use the Mod/RM byte
+    /// to specify a source, which in this case is a register.
+    ///
+    MRMSrcReg      = 4,
+
+    /// MRMSrcMem - This form is used for instructions that use the Mod/RM byte
+    /// to specify a source, which in this case is memory.
+    ///
+    MRMSrcMem      = 5,
+  
+    /// MRMS[0-7][rm] - These forms are used to represent instructions that use
+    /// a Mod/RM byte, and use the middle field to hold extended opcode
+    /// information.  In the intel manual these are represented as /0, /1, ...
+    ///
+
+    // First, instructions that operate on a register r/m operand...
+    MRMS0r = 16,  MRMS1r = 17,  MRMS2r = 18,  MRMS3r = 19, // Format /0 /1 /2 /3
+    MRMS4r = 20,  MRMS5r = 21,  MRMS6r = 22,  MRMS7r = 23, // Format /4 /5 /6 /7
+
+    // Next, instructions that operate on a memory r/m operand...
+    MRMS0m = 24,  MRMS1m = 25,  MRMS2m = 26,  MRMS3m = 27, // Format /0 /1 /2 /3
+    MRMS4m = 28,  MRMS5m = 29,  MRMS6m = 30,  MRMS7m = 31, // Format /4 /5 /6 /7
+
+    FormMask       = 31,
+
+    //===------------------------------------------------------------------===//
+    // Actual flags...
+
+    /// Void - Set if this instruction produces no value
+    Void        = 1 << 5,
+
+    // TB - TwoByte - Set if this instruction has a two byte opcode, which
+    // starts with a 0x0F byte before the real opcode.
+    TB          = 1 << 6,
+
+    // FIXME: There are several more two byte opcode escapes: D8-DF
+    // Handle this.
+
+    // OpSize - Set if this instruction requires an operand size prefix (0x66),
+    // which most often indicates that the instruction operates on 16 bit data
+    // instead of 32 bit data.
+    OpSize      = 1 << 7,
+
+    // This three-bit field describes the size of a memory operand.
+    // I'm just being paranoid not using the zero value; there's 
+    // probably no reason you couldn't use it.
+    MemArg8     = 0x1 << 8,
+    MemArg16    = 0x2 << 8,
+    MemArg32    = 0x3 << 8,
+    MemArg64    = 0x4 << 8,
+    MemArg80    = 0x5 << 8,
+    MemArg128   = 0x6 << 8,
+    MemArgMask  = 0x7 << 8,
   };
 }
 
@@ -30,9 +105,16 @@ public:
   ///
   virtual const MRegisterInfo &getRegisterInfo() const { return RI; }
 
-  /// print - Print out an x86 instruction in GAS syntax
+  /// print - Print out an x86 instruction in intel syntax
   ///
-  virtual void print(const MachineInstr *MI, std::ostream &O) const;
+  virtual void print(const MachineInstr *MI, std::ostream &O,
+                     const TargetMachine &TM) const;
+
+  // getBaseOpcodeFor - This function returns the "base" X86 opcode for the
+  // specified opcode number.
+  //
+  unsigned char getBaseOpcodeFor(unsigned Opcode) const;
+
 
 
   //===--------------------------------------------------------------------===//